Plug-n-play UVM Environment for Verification of Interrupts in an IP

By Shalini Damani, Tejbal Prasad (Freescale Semiconductor)

Abstract

In a System-on Chip(SoC),a general interrupt process works as follows:- a) Interrupt is triggered by a certain system event or interrupt source. b) Interrupt is detected by system’s peripheral module, which then asserts its interrupt output pin and set its interrupt status register at the same time. c) Interrupt is captured by the embedded processor and an interrupt routine is executed to process the interrupt d) After processing the interrupt, interrupt status is cleared by writing related interrupt registers within the peripheral module. And the module is ready for another interrupt. e) Additionally in ISR (Interrupt Service Routine), any register related to that interrupt status is checked for the correct behavior. In a standalone IP verification environment, usually the practice is to clear the status as soon as they are set. This paper proposes a method to mimic the actual behavior of the embedded processor for interrupt handling in standalone IP verification environment. Use of UVM components done to make a reusable, parameterizable and real time interrupt handler for UVM testbench. The method proposed in this paper describes an automated interrupt handler logic which runs parallel to entire environment.