Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP

By Shalini Damani, Sunny Aggarrwal (Freescale Semiconductor)

Abstract

With the declining gate length in new process technologies, static power dissipation becomes a bigger problem. Nowadays, power is replacing performance as the key competitive metrics in SoC. This triggers the need for multi-voltage management techniques.CPF or Common Power Format provides techniques and concepts that can be applied at various stages throughout low-power SoC design development to express the power intent of an IC design.