IP Exchange Through Handoff for Easy System-On-Chip Design

By Rahul Kheterpal, Atul Nauriyal, Vivek Sinha (STMicroelectronics Pvt.Ltd)

Abstract

Over the past ten years, as integrated circuits became increasingly complex and expensive, the industry began to embrace new design, reuse and optimisation methodologies for doing System-on-Chip (SoC) design. Design of such SoCs typically relies on multi-team, multi-site cooperation and data exchange. Intellectual Property (IP) Reuse is one of the keys for SoC design efficiency improvement; so alongside designing IPs, it is very important to be able to put them to appropriate use in future designs. This has also been extended to SoC subsystem exchange. This paper provides insight into a novel solution used to build SoCs targeting increased productivity in a complex environment. It describes the IP exchange and checking infrastructure deployed in a live design environment to ensure a well-timed and transparent transference of the sub-systems from the handoff to the implementation team. The solution targets an automation-capability which plays a vital role in extracting from the design repositories the relevant IP files and automatically performs the environment creation necessary for executing design handoff checks in-situ. This paper describes a design-automation method which emphasises on eliminating human intervention each time a design is to be re-introduced, ensures easy top-level absorption, parallel debugging and group handling of several IPs, thus guaranteeing schedule savings. The first section will present an introductory overview of the handoff process and the recommended method will follow in detail later. The subsequent sections depict the working model as well the benefits of the approach. Necessary observations and statistics to justify the benefits are also provided. Further scope of extension is also addressed.