What an FPGA Vendor Knows about IP Reuse

By Ron Wilson (Altera)

Abstract

An FPGA vendor depends on a vast library of its own and partners' IP in a world of constant process migration and architectural evolution, and of stark distinctions between hard and soft IP. And it gets feedback from literally thousands of different real designs. So it is an ideal laboratory in which to learn the realities of IP reuse. Among the lessons: process migration is mostly a myth; the trade-offs between performance, efficiency, and flexibility are more complex than many users can appreciate; IP assembly easily becomes redesign; and new categories of IP beyond hard and soft have become vital to tomorrow's designs.

Biography

Formerly the editorial director of ESD magazine, Embedded.com, and Embedded Systems Conferences, Ron Wilson now works for Altera. *He has over 38 years of experience in the electronics industry. He held a variety of editorial positions within EE Times from 1991 to 2006. Wilson also served as a writer and the publisher of ISD Magazine and has written and edited for EDN Magazine and Computer Design. Wilson also has experience in design engineering, evaluation, customer training, market research, product marketing and marketing management. In addition, Wilson's work has been published in a variety of media, including newspaper and magazine articles, portions of two books on electronics and a long-running Blog on SoC design for EDN. Additionally, Wilson is a pioneer in the electronics marketplace. He created the first virtual event in 2002 entitled "SOC-Online" and created the EETimes Industry Challenge series addressing key issues in electronics which incorporated research, print online and live events.