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IP Camera Front End

Configurable CAN Bus Controller with Flexible Data-Rate

• Designed in accordance with ISO 11898‐1:2015 specification
• Supports CAN and CAN FD frames
• Supports up to 64 bytes of data frame

Enhanced Multiprotocol Serial Communication Controller

• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction

DCD's Universal Timers System

Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s

• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction

SMBUS & PMBUS Master/Slave controller

• Master operation: Master transmitter, Master receiver
• Slave operation: Slave transmitter, Slave receiver

UART Core with SDLC Function

RSA-ECC High-Performance Multi Public Key Engine

• RSA, ECC and more
• > 1 GHz in 16nm

TicoXS FIP UHD8K Encoder / Decoder IP-core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency !

TicoXS FIP UHD4K Encoder / Decoder IP-core with JPEG XS and Flawless Imaging Profile (FIP) - – The newest codec for AV over IP with 100% quality and zero latency !

• Extremely low footprint in FPGA or ASIC (low logic, low memory, low DDR)
• Compliant with JPEG XS High Profile & Flawless Imaging Profile (FIP)

IrDA Controller

• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction

I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)