Date 2002 conference to spotlight IP, SoC issues

Date 2002 conference to spotlight IP, SoC issues
By Nicolas Mokhoff, EE Times
February 11, 2002 (6:16 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020211S0086

MANHASSET, N.Y. — Intellectual property for use in system-on-chip designs will be a major topic at this year's Design Automation and Test in Europe (Date) conference. Slated for March 4-8 at the Palais des Congrès in Paris, the Date conference and exhibition will devote one day each, March 5 and 6, to IP and SoC issues, respectively.

IP Day, organized by Yervant Zorian, chief scientist at Virage Logic (Fremont, Calif.), will include the topics, "How to Choose Semiconductor IP" and "What is the Right IP Business Model." In the first panel, participants representing different IP market segments, drawn from ARM, Cadence, ChipIdea, Mentor Graphics, Virage Logic and VSIA, will discuss the criteria for choosing semiconductor IP, including interoperability, flexibility, optimization, validation, portability, retargetability, manufacturability and certification.

In the IP Business Model session, analysts from AH&H, Dean Rauscher Wessels, Deci sive Technology Research, Gartner Group and Soundview will explore the different business models IP providers have experimented with. The analysts will forecast the future of the IP market and discuss the "right" IP business models to make this sector viable again.

Meanwhile, an embedded tutorial, "The Need for Infrastructure IP in SoCs," will offer a forum for presenters from HPL Technologies, Iroc, LogicVision and Virage Logic. With very deep-submicron semiconductor technologies of 0.13 micron and below, SoCs have reached susceptibility levels that would put semiconductor reliability, diagnosis and yield at risk, if they were based on conventional processes. The speakers will give their take on embedded test and repair and the yield, diagnosis and robustness of IP.

Keynotes

Hugo De Man of IMEC, Belgium, will deliver the first keynote, "Nanoscale Integration and Gigascale Complexity in the Post.com World" on Tuesday, while Taylor Scanlon, CEO of Virtual Silicon Technology (Sunnyvale, Calif.), will present his keynote, "Global Responsibilities in SoC Design," on Wednesday.

One of the most provocative sessions is expected to be the CTO panel, where chief technology officers Wally Rhines of Mentor Graphics, Raul Camposano of Synopsys, Ted Vucurevich of Cadence and Frank Neppl of Infineon will look at the challenges facing both the electronic design automation industry and the customers who rely on it.

Another important IP-based issue — "Who Owns the Platform?" — will be debated at the panel. Panelists will be asked to take a look at the full range of vendors, from IP houses, fabless semiconductor companies and traditional companies, and predict which will be in charge of developing the platforms of the future.