IBM exec calls for system-level tools
![]() | |
EE Times: IBM exec calls for system-level tools | |
Richard Goering (04/07/2005 11:36 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=160502670 | |
MONTEREY, Calif. Design automation needs to provide an integrated approach to system-level design, said John Darringer, manager for system-level design at IBM's T.J. Watson research center, in a keynote speech at the Electronic Design Processes (EDP) workshop here Thursday (April 7). Darringer also called for merging the "best" of the ASIC and processor design methodologies, and outlined a design approach for future "servers on a chip" that IBM intends to build. Darringer showed how business trends are placing pressure on systems designers to increase parallelism, exploit low-latency communications, accelerate tasks, build scalable systems, and reduce cost of ownership. System design is becoming more complex and is demanding an analysis of tradeoffs, workloads, and new software architectures, he said. "If you look at the tools experts use, they're typically spreadsheets," he said. "Then they team up with people who build some custom models." These include technology models for energy, power, timing, and yield, along with performance models for cores, caches, busses, I/Os, and memories. The trouble is that these models are written by different individuals, and they have no connection to one another. Then there is, at best, a "vague handoff" to RTL design, based on various documents. "Power, performance, and interconnect models all have unique representations. They don't even have compatible inputs and outputs. We've got to fix that. I need a way to bring these models together," Darringer said. The need is especially great, Darringer said, because of the growing complexity of tradeoffs with the advent of multiple threshold voltages, clock and power gating, voltage islands, asynchronous design, and other new techniques. One approach that's gained some attention is "globally asynchronous, locally synchronous" (GALS) design. But GALS design raises a number of questions, Darringer noted. How many partitions, what's the best place to partition, what's the synchronization penalty? "If you look at the traditional models within IBM to do this, you could modify them forever," he said. "I need a way to do this quickly." "I'm not saying we need new performance modeling techniques," he said. "We have good techniques. But the frustrating thing is that the work is not connected to work done by other teams." In addition to a more integrated modeling approach, a direct transfer to RTL is needed, Darringer said. He suggested this could be facilitated by extending the OpenAccess database to architectural design. Darringer also spoke of the need for modeling at intermediate levels, with formal verification used between the levels. Darringer also noted growing similarities between ASIC and processor design. "In my view the server guys are heading to the same place as the processor guys," he said. "Both have more cores, I/O, memory, and accelerators. A common bus structure will probably emerge that brings these guys together." Future servers-on-a-chip, he said, will involve system-level assembly, "efficient" custom design, synthesis of non-custom components, accurate planning for power and timing, and automatic chip integration. One thing that's common to both IBM ASIC and processor design, Darringer noted after the keynote, is a reliance on internal tools. "We're always trying to figure out how to take advantage of vendor tools, but IBM is very strong on developing internal tools," he noted. EDP, now in its twelfth year, is a two-day IEEE-sponsored workshop focusing on electronic design methodologies.
| |
- - | |
Related News
- CoWare tailors system-level tools to developers, users
- Is system-level the next wave in EDA tools for SoCs?
- Tool vendors Synplicity Inc. and Forte Design Systems Inc. bring system-level tools to PLD masses
- Agilent Technologies' New Electronic System-Level EDA Platform Helps Algorithm Developers, System Architects Cut Design Time in Half
- Synopsys Adds 30 New Titles to DesignWare System-Level Library
Breaking News
- VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system
- Avant Technology Partners with COSEDA Technologies to Enhance System-Level Software Solutions
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Sarcina Technology launches AI platform to enable cost-effective customizable AI packaging solutions
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |