AccelChip Announces AccelCore IP Core Product Line

Company Offers First Stand-alone RTL Cores for Linear Algebra

MILPITAS, CA, April 13, 2005 – AccelChip Inc., the industry’s only provider of automated flows from MATLAB® algorithms to silicon, has become the industry’s first company to provide fixed-point linear algebra intellectual property (IP) as stand-alone RTL cores. Initial offerings provided in the new AccelCore™ product line include matrix inverse and factorization cores used in applications such as beamforming, software-defined radio, radar/sonar, Kalman filtering, and other wireless applications.

I ntended for algorithm developers and hardware designers who are retargeting software algorithms to FPGAs and ASICs, AccelCore IP cores deliver synthesizable, pre-verified DSP functions for rapid development designs requiring matrix inversion or factorization. The VHDL/Verilog cores are highly optimized in terms of speed, power, and size. They have been fully synthesized and validated on Xilinx (NASDAQ: XLNX) and Altera (NASDAQ: ALTR) FPGAs.

Until now, performing matrix factorization and inversion in hardware has been difficult because the algorithms are complex and highly sensitive to numerical problems, particularly when using fixed-point arithmetic preferred in high-performance ICs. As a result, most designers have been compelled to implement these linear algebra algorithms in C on DSP or general-purpose processors. The demands of new linear algebra applications are increasing the demand for IP cores that can achieve higher performance and reduce form factors attainable by integrating DSP capabilities in FPGAs and ASICs.

“Matrix factorization and inversion are used with algorithms utilizing linear algebra techniques, such as adaptive filters, which are used in a wide range of applications from radar to global positioning. AccelCore IP cores are off-the-shelf, pre-verified DSP cores that negate the need for designers to write their own core in VHDL or Verilog, then build a testbench to verify the model,” said Michael Bohm, CTO and vice president of Engineering, AccelChip. “AccelCore matrix cores are truly the first of their kind in the industry, and they can save customers months of RTL coding.”

The first release of AccelCore IP cores from AccelChip performs matrix inversion and factorization using two methods – triangular-orthogonal factorization, or QR factorization, as well as Cholesky factorization. QR factorization provides a robust, general method while Cholesky factorization provides a faster, more compact core for certain classes of applications. Evaluation copies of each AccelCore IP core are available and utilize ModelSim® to test and simulate the functionality, speed, and FPGA resource utilization and allocation, allowing the user to observe how the cores will perform in a complete design. For more information and datasheets on the cores, please visit www.accelchip.com/products.

About AccelChip

AccelChip Inc. is the industry’s only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip’s proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com.

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AccelChip, AccelWare, and AccelView are registered trademarks of AccelChip Inc. AccelCore is a trademark of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.

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