IN2FAB releases OSIRIS for analog circuit porting and reuse

In2Fab (Buckinghamshire, England) said its Osiris series of tools, based on patented "complex nodal scaling" technology, is capable of porting complex analog circuits between process geometries while maintaining exact hierarchical and topological relationships throughout the circuit.

For example, In2Fab said, Osiris retargeted a phase-locked loop (PLL) from 130 nm CMOS to 90 nm CMOS with two-and-a-half hours of setup time, 10 minutes of processing and three days of analysis and adjustment. According to Robert Baker, In2Fab CEO, retargeting a similar design using a traditional approach would take between one and two months—about a week to redraw schematics and then four-to-six weeks to layout the device. Overall, Baker said, In2Fab consistently sees time reduction of greater than 10X with Osiris.

"The bottom line," Baker said, "is that the device will be ported with Osiris in a total cycle time of hours-to-days, compared to the many weeks and months using a traditional methodology."

Baker said the Osiris retargeting process is highly automated. He said human input is required in set up—filling in forms if not already done—and for some backend adjustments.

Baker said Osiris takes the original design and automatically moves it topologically and hierarchically exactly to the new process rules. "If there is a geometry change, for example 180 nm to 130 nm, then the design can be scaled to achieve optimal die size," he said. "This is where it gets interesting because rules—and there are many of them—do not scale linearly. Each has to be handled on its merits and Osiris works out what can be scaled and by how much while maintaining topology. This is all automatic."

According to In2Fab, Osiris tools have also been used to migrate large analog centric application chips and custom designs such as ARM cores. Baker said In2Fab has not hit a limit in terms of the size of cores that Osiris can retarget. "On one end of the scale we have regularly migrated ARM7 and ARM9 cores with 2.7 million transistors to all sorts of different processes without difficulty," Baker said.

Baker said there are currently two other options for analog retargeting—manual redesign using the same schematic-driven method as the original, or compaction, which is problematic for analog because by its nature it breaks down circuit topology, hampering performance. He said that Osiris is superior as an automated capability because it was built specifically for analog, retains topology and maintains hierarchy exactly and is not limited by known design size.

"The design proposition is dramatic reduction of the cycle time to reuse analog IP rather than being forced to re-create it," Baker said. He added that Osiris can enable faster time to market, require fewer skilled designers and reduce development costs, among other benefits.

Baker said In2Fab is currently working at the 65-nm node with a European integrated device manufacturer (IDM) that wants to make available a number of its analog and mixed signal modules to its business units for system-on-chip (SoC) development. Using Osiris, Baker said, will allow the company to complete all of this work during the current quarter. The IDM had previously estimated that it would take a design team more than one year to recreate this IP at a different process node, he said.

The company said Osiris works within Cadence Design Systems' Analog Artist analog design environment and Design Framework II and directly supports foundry process design kits. Osiris is able to scale, migrate and adjust the physical design in Cadence format or GDSII and can also retarget schematics and netlists like Spice, the company said.

In2Fab said it has developed and matured Osiris over many years to provide analog porting services for a range of customers. The company said Osiris is widely silicon proven with numerous successful tapeouts.

Founded in 1999 as Design Resources, In2Fab originally operated as a physical layout and process migration services firm before entering the market with its first EDA tools for interconnect-specific incremental synthesis in July 2003.