Major New Release of Synfora PICO Express Cuts Time and Cost Of Producing Complex Consumer System-on-Chip Designs

Mountain View, Calif. — April 26, 2005 — SynforaTM, Inc. announced the 5.01 release of PICO ExpressTM for application engine synthesis (AES), which is used to greatly accelerate the design of systems-on-chips (SoCs).  The new release features enhanced capabilities for solving implementation challenges inherent in state-of-the-art algorithms found in multimedia (H.264, WMV), imaging (photo-quality printing), wireless (3GPP), and security (AES) applications.  PICO Express empowers electronic system-level (ESL) design methodologies by creating flow-controlled networks of hardware accelerators from sequential C algorithms.  This addresses the critical issue of complexity levels typical of algorithms such as H.264.

 “Many companies are working to implement complex algorithms in silicon, for example, H.264 encoders, and they are challenged by unprecedented design complexity,” said Synfora CEO Simon Napper.  “It’s not enough to move to a higher-level language; they need to move to a higher-level capability.  The unique ability of PICO Express to take complex C algorithms and automatically create an efficient, flow-controlled network of hardware accelerators is crucial for managing this implementation complexity.  PICO Express 5.01 is the only tool that can produce designs with that complexity.”

Thierry Bauchon, Director of R&D for the Home Entertainment Group of STMicroelectronics, said, “We have used PICO Express on two occasions to produce RTL code used in recent design tape-outs.  The first time, Synfora ran the tool and provided RTL to us.  The results were competitive and the RTL was delivered much faster than the time forecast for a design by hand.  More than one year later, our requirements changed, and we were able to pick up the original C algorithm and make the required changes in less than a day.  PICO Express helped us to meet our tapeout deadlines with silicon optimized for our highly competitive markets.” 

About PICO Express 5.01
PICO Express 5.01 expands the networks of hardware accelerators that can be synthesized from C algorithms.  It also broadens the scope of algorithms that can be efficiently synthesized by blending highly pipelined and sequential stages that are typically found in advanced algorithms such as H.264, WMV, and 3GPP.  As a result, designers can now create more sophisticated networks of hardware accelerators.

PICO Express 5.01 automatically analyzes sequential code blocks to determine if they should run sequentially or in parallel.  For performance targets that require further parallelism, multiple buffers will be inserted automatically for shared arrays to allow multiple tasks to run in parallel.  In addition, PICO Express 5.01 supports data paths greater than 32-bits by supporting co-scheduling of multiple streams of data.

With PICO Express 5.01, design teams can now leverage the benefits of SystemC for system-level validation without needing to learn the vagaries of the language.  PICO Express automatically generates SystemC “wrapped” models at multiple levels, for accurate modeling and validation of a network to hardware accelerators within the system context.  PICO Express also supports SystemC and Verilog RTL co-simulation.  The co-simulation of RTL with SystemC lets a designer analyze the detailed parallelism of the RTL, and validate the multi-threaded interface between the hardware accelerator and the application processor.

PICO Express 5.01 now also gives designers improved correspondence between C and RTL.  This is beneficial when there are concerns about engineering change orders, and when a designer wants to understand what the compiler has done so as to improve the input code.  The compiler in PICO Express performs powerful analyses and extensive optimization to exploit parallelism and find the most efficient implementation.  The improved correspondence eases the mapping of C operators and variables to RTL constructs.

PICO Express 05.01 continues to leverage the benefits of its unique PPA architecture to ensure first pass-timing and physical closure, and automatic creation of a thorough unit-level verification test bench.   

About Synfora, Inc.
Founded in 2003, Synfora, Inc. of Mountain View, Calif. is the leading provider of application engine synthesis (AES) software used to design complex systems-on-chips (SoCs).  Synfora’s patented technology helps to reduce fixed design costs and dramatically speed chip development and time-to-market.  Synfora targets companies in the audio, video, imaging,  wireless, and security segments of the IC design market.  The company’s investors are ATA Ventures, Foundation Capital, and U.S. Venture Partners.  For the latest news and information on Synfora, visit www.synfora.com.