English
FPGA Design Needs More Than a Face Lift
By Simon Bloch, Mentor Graphics -- Electronic News, 4/27/2005
FPGA design success is based on the promise of getting to hardware fast, while performing system debug on actual hardware. Constant re-spins, including architectural/design changes, are performed until the FPGA meets system requirements. This method works for smaller devices, but obviously fails for high-end FPGAs because the resulting unpredictable design schedules imply unacceptable product slippages and unrealized business.
Related News
- Gidel Launches Lossless Compression IP that Reduces Storage Needs by Over 50%, Utilizing Only 1% of the FPGA, with Low Power Consumption
- Intel FPGA Technology Supports NEC in Face Recognition Technology
- STMicro face-recognition processor includes FPGA core
- Achronix Releases Groundbreaking Speedster AC7t800 Mid-Range FPGA, Driving Innovation in AI/ML, 5G/6G and Data Center Applications
- RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs
Breaking News
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |