English
FPGA Design Needs More Than a Face Lift
By Simon Bloch, Mentor Graphics -- Electronic News, 4/27/2005
FPGA design success is based on the promise of getting to hardware fast, while performing system debug on actual hardware. Constant re-spins, including architectural/design changes, are performed until the FPGA meets system requirements. This method works for smaller devices, but obviously fails for high-end FPGAs because the resulting unpredictable design schedules imply unacceptable product slippages and unrealized business.
Related News
- Gidel Launches Lossless Compression IP that Reduces Storage Needs by Over 50%, Utilizing Only 1% of the FPGA, with Low Power Consumption
- Intel FPGA Technology Supports NEC in Face Recognition Technology
- STMicro face-recognition processor includes FPGA core
- Achronix Releases Groundbreaking Speedster AC7t800 Mid-Range FPGA, Driving Innovation in AI/ML, 5G/6G and Data Center Applications
- RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |