Low-power design goes mainstream
EE Times: Low-power design goes mainstream | |
George Kuo (05/16/2005 10:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=163101933 | |
Advanced process technologies, rising clock rates and increased circuit complexity have meant an end to traditional methods of managing power consumption. Engineers can no longer expect to achieve power-efficient designs with a quick power calculation and a liberal dose of decoupling capacitors. Instead, they need to routinely apply sophisticated low-power design methods that can address the rising impact of power problems in nanometer designs at 130 nm and below. In the past, low-power design specialists have used such techniques as clock gating, frequency scaling, novel processes or libraries, and even more-sophisticated techniques such as voltage scaling and multithreshold cell optimization. For the typical designer, however, many of these methods have been relatively inaccessible or impractical. In graph of performance vs. voltage scaling and Vth trade-off, the most power-efficient cell, 0.8-V HVt cell, has almost 2.5x delay impact vs. standard cell at 1 V.The growing availability of enhanced tools, models and processes-all highly matched and expressly created for low-power design-has begun to put more-effective low-power design capabilities in the hands of mainstream designers. Today, successful strategies for low-power design are extending familiar design flows with more-effective models, detailed analysis techniques and careful consideration of effects like IR drop and electromigration. In using these power-optimized design flows, designers will need to adhere to several key design principles found through experience to significantly enhance low-power design success. Do
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George Kuo (gkuo@cadence.com), engineering director for design chain initiatives at Cadence Design Systems Inc.(San Jose, Calif.)
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