CEVA Unveils a New Addition to the Powerful CEVA-X DSP Family

The CEVA-X1621(TM) Combines the High Performance Level of the CEVA-X1620(TM) DSP Core with an Advanced Cache Memory Subsystem

SPRING PROCESSOR FORUM - SAN JOSE, Calif. - May 16, 2005 - CEVA, Inc. (NASDAQ: CEVA; LSE: CVA), the leading licensor of digital signal processing (DSP), multimedia and communications platforms to the semiconductor industry, today unveiled the newest addition to its licensable CEVA-X(TM) DSP architecture - the CEVA-X1621(TM). The CEVA-X1621 combines the high performance of the CEVA-X1620(TM) DSP with an advanced, configurable cache memory subsystem. The CEVA-X1621 targets System-on-a-Chip (SoC) designs for next-generation products including 3G handsets, smartphones, portable media players, digital televisions, internet protocol television (IPTV) and set-top boxes.

The CEVA-X1621 is a high-performance, low-power, fully synthesizable DSP offering several key benefits, including:

• small die size and low cost - by reducing the amount of on-chip memory; application memory size can be reduced as much as 50 percent
• low power consumption - using smart power management mechanisms to reduce memory consumption, systems can achieve longer battery life and better heat dissipation
• customizable - the DSP can be configured to meet different performance, area and power consumption targets
• shorter time to market - transparency of memory architecture simplifies and accelerates software development
• integrated multimedia support - dedicated multimedia instructions and mechanisms greatly accelerate video and image processing.

"CEVA-X1621 addresses key challenges for the upcoming generation of mobile and home entertainment products," said Will Strauss, founder and president, Forward Concepts. "The CEVA-X1621 combines the proven performance of the CEVA-X1620 DSP with an advanced cache memory subsystem to accommodate customers who need a high-performance, low-power DSPs with decreased die size and cost. The cache subsystem built into the CEVA-X1621, enhances the processor's inherent support for OS and control functions, in addition to signal processing."
 
The newly-developed memory subsystem features custom configurations that include level-one (L1) data and instruction caches and an optional level-two (L2) unified cache, as well as optional L1 and L2 local memories, all available in multiple sizes.  Performance enhancements include support for miss-pipelining, non-blocking L2 unified cache and deterministic hardware and software pre-fetches. The system also supports fast data transfers minimizing memory stalls. Multimedia support is provided by two-dimensional (2-D) cache pre-fetches along with 2-D DMA transfers. Memory protection provides software stability and security.
 
The CEVA-X1621 DSP features a 16-bit fixed-point dual-MAC very long instruction word (VLIW) architecture combined with a single instruction multiple data (SIMD) multimedia operation, up to eight instructions executed in parallel, variable instruction widths (16-bit or 32-bit) and  4GB of byte-addressable memory space. A wealth of multimedia instructions and mechanisms built into the architecture enable the processor to dramatically accelerate advanced video compression standards, such as MPEG4 and H.264, on a pure software platform. Moreover, the innovative reusable architecture of the CEVA-X provides customers complete deployment flexibility within a unified architecture framework.
 
"Our continued investment in the CEVA-X product family underscores our commitment to the ongoing development of dynamic and configurable DSP technology that caters to the specific needs of our customers' markets," said Gideon Wertheizer, CEO of CEVA, Inc. "The addition of the CEVA-X1621 to our DSP roadmap will further strengthen our position as a leader in providing multimedia, communication and DSP solutions to semiconductor manufactures."
 
More details on the CEVA-X1621 DSP core will be unveiled at Spring Processor Forum, taking place in San Jose, Calif., May 16-19.  CEVA will present on Wednesday, May 18 during the "Advances In DSP Engines" session.  More information on CEVA and its products can be found at www.ceva-dsp.com.
 
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is the leading licensor of DSP, communications and multimedia solutions to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including video processing, audio processing, speech processing, GPS location, Serial-ATA (SATA) and VoIP. In 2004, CEVA's silicon IP was shipped in more than 100 million devices. CEVA was created through the merger of the DSP licensing division of DSP Group and Parthus Technologies. For more information visit www.ceva-dsp.com