CEVA and Ignios Demonstrate Multicore DSP

Ignios Joins CEVAnet, Enabling Multicore DSP System Design for CEVA Licensees First SystemWeaver Demonstration to Feature Dedicated DSP Core

SAN JOSE, Calif. and Oxford, UK - June 9, 2005 - CEVA, Inc. (NASDAQ: CEVA; LSE: CVA) the leading licensor of digital signal processors (DSP) cores, multimedia, GPS and storage platforms to the semiconductor industry, and Ignios Ltd., a provider of semiconductor IP for the multicore System-on-Chip (SoC) market, today unveiled a reference platform that demonstrates multiple CEVA-Teak™ DSP cores seamlessly operating together using Ignios' multicore-enabling SystemWeaver™ technology.

The demonstration platform brings together up to 16 CEVA-Teak DSP cores, with the capability for further scalability, and the SystemWeaver multicore management core in a representative SoC architecture. With the SystemWeaver approach, the software developer is presented with the same multi-threaded programming model (API) no matter how many processors are present in the SoC, considerably easing multicore software development and debug. The SystemWeaver IP core ensures that the resulting code executes efficiently on the available processing resources. This approach can be similarly utilized for CEVA-X™ or other homogenous or heterogeneous combinations of CEVA DSP cores.

Licensees of CEVA DSP cores and platforms who adopt SystemWeaver would benefit from the ability to easily develop and deploy multicore designs, a growing requirement for compute-intensive cellular basestations and high channel density VoIP gateways. With SystemWeaver, code can easily be developed on a single processor and then quickly retargeted to all of the devices using dynamic and flexible scheduling policies for different classes of task and processing resource.

The platform, developed in merely two weeks by Ignios using the ARM® RealView® Electronic System Level (ESL) tools with MaxSim™ technology, demonstrates the ability to easily explore and then efficiently program a multicore DSP architecture to achieve the best possible price-performance-power characteristics for an application.

"We are seeing increasing demand for our advanced DSP IP solutions in multicore implementations," commented Moshe Sheier, CEVA director of Third Parties and Technical Marketing. "The SystemWeaver approach provides an extremely efficient way for our customers to get the best out of combining multiple CEVA cores on the same SoC. Ignios will be an important addition to our CEVAnet partner program."

"We are delighted to be working with CEVA to enable their customers' multicore SoCs," stated Rick Clucas, Ignios CEO. "SystemWeaver has been designed to support homogeneous and heterogeneous multicore SoCs. This demonstration platform clearly shows that SystemWeaver is compatible with an industry leading DSP architecture."

Ignios will be demonstrating the CEVA-based system model at the 42nd Design Automation Conference, Anaheim, Calif., June 13-16, at booth 261 www.dac.com.

SystemWeaver addresses the software and hardware challenges presented by the proliferation of all multicore architectures - simple and complex - in the embedded chip market. The SystemWeaver API provides a unified abstraction layer for complex multicore devices. This abstraction allows embedded systems companies to develop and debug multicore applications more effectively, improving time to market. The key underlying system management and communications functions are implemented natively in a SystemWeaver IP core that is integrated on-chip. SystemWeaver unlocks the full performance of the multicore hardware, with significant cost, power and performance benefits that maximise product competitiveness.

SystemWeaver release v1.0 is available now and consists of the parameterisable, synthesisable SystemWeaver IP core and the SystemWeaver API. A SystemC model of the core and reference models of SystemWeaver-enabled SoCs are also provided.

Ignios was established in 2003 to develop and market products that enable the real-time on-chip system management of multicore SoC devices. Ignios raised a total of $3.8 million in a first round of private financing early in 2004. The funding round was jointly led by Alice Lab and BTG. Further information on Ignios can be found at www.ignios.com.

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