TSMC Reference Flow 6.0 Opens Door to 65nm Design

Features Unique Advances in Power Management through Methodology and Library Integration     
        
SAN JOSE, CA – June 9, 2005 -- Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), today introduced Reference Flow 6.0, that provides state-of-the-art access to TSMC's 65nm process technology. The new Reference Flow includes innovative power management features in a comprehensive electronic design automation (EDA) methodology that is supported, for the first time, by seamlessly integrated, low-power TSMC libraries. In addition, Reference Flow 6.0 provides new design for manufacturing (DFM) capabilities for faster yield ramps and increased return on investment. “As the IC industry migrates to 65nm technology, the two leading design requirements are low power and faster return on investment,” said Edward Wan, senior director of design service marketing for TSMC. “Collaborating with the EDA industry, TSMC’s Reference Flow 6.0 addresses these demands through power management and DFM techniques, while at the same time lowering the entry barriers for designers of leading-edge products using advanced processes.” In addition to power management and DFM, Reference Flow 6.0 provides a wide range of additional enhancements including half node migration, design-for-test (DFT), integrated chip-and-package design, hierarchical dynamic voltage drop analysis, and hierarchical crosstalk analysis. Through extensive collaboration with Apache, Atrenta, Cadence Design Systems, Inc., Mentor Graphics Corp., Optimal and Synopsys, Inc.,TSMC has anticipated pressing design challenges and developed timely services to address them. “Reference Flow 6.0 is a significant milestone in the ongoing design chain collaboration between Cadence and TSMC to accelerate nanometer design,” said James Miller, Jr., senior vice president, Development at Cadence. “Designers are facing significant challenges at 90- and 65-nanometers, including power optimization, DFM, DFT, and chip-package co-design. We're pleased to collaborate with TSMC in Reference Flow 6.0 to address these key issues by leveraging the innovative technologies within the Encounter™ and Allegro™ design platforms.” “Synopsys and TSMC have been collaborating since Reference Flow 1.0 to address the latest design challenges for each successive process generation,” said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. “At the 90nm and 65nm processes, Design for Manufacturing (DFM), power optimization, and better yield are mission-critical needs. Through our collaboration and the Galaxy™ Design Platform, we deliver advanced features to address these challenges in TSMC Reference Flow 6.0.”         
        
Power Management         
        
Building upon the company's pioneering power closure methodology in Reference Flow 5.0, which brings both power optimization and power integrity into the design practice, Reference Flow 6.0 further drives down power consumption through an advanced methodology and seamlessly integrated low-power libraries targeting TSMC's advanced low power processes. The result is a “global optimization” of process, design methodology and libraries. This global optimization stands on two legs: advanced voltage scaling to manage dynamic power; and unique power gating techniques to mitigate leakage power. Reference Flow 6.0's voltage scaling capability provides support for multiple voltage islands. This allows design partitioning into power-isolated blocks; and achieves power saving by setting different supply voltages for each block based on specific performance requirements. Supply voltages for each block can be changed dynamically for variable performance requirements. This provides flexibility to take advantage of the full range of dynamic power saving opportunities. To effectively mitigate leakage power, Reference Flow 6.0 features a unique power gating technology utilizing the multi-threshold CMOS (MTCMOS) design structure. By inserting MTCMOS high Vt footers to shut down the circuits that are not operating, designers can cut the leakage by 90 percent or more, depending on the implementation being used. TSMC is offering a fine-grained MTCMOS technology initially, to be followed by a coarse-grained technology for even greater leakage reduction. For both the voltage scaling and power gating techniques, TSMC provides data retention flip-flops to store the data during power-down and to ensure the circuits function normally at wake-up. Libraries are key power management enablers. Voltage scaling requires level shifters, isolation cells, and standard cell libraries that are characterized for multiple voltage corners. The libraries support effective current source models (ECSM) and composite current source models (CCS). For power gating, a new set of low Vt and standard Vt cells with high Vt footers inserted into them, is required. Additional timing and leakage characterization is also required for the cells of this new structure. TSMC has addressed all of these requirements with its new low power Nexsys libraries. Design for Manufacturing (DFM) At the 65-nanometer technology node, process variance and pattern sensitivity are emerging as major yield influencers. The need to ensure accurate information flow between design and manufacturing is clear. Reference Flow 6.0 follows the tradition of the previous generations by offering key DFM enhancements to improve yield. A new metal fill utility increases metal density and improves metal density uniformity throughout the device. In addition, half-track wire spreading is made available for the first time, to distribute wire more evenly. Some of the earlier 90nm DFM guidelines are now part of design rules in 65nm in addition to new 65nm design rules. TSMC has also worked with EDA partners to embed the OPC-friendly guidelines into commercial tools, ensuring that leading EDA tools support 65nm design rules through rigorous testing with multiple test cases.         
        
About TSMC        
        
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.