Spiral Gateway preps C-programmable low-power fabric

If the claim stands up the technology is potentially disruptive and could help change hardware design into a peripheral consequence of software programming.

The architecture, named Reconfigurable Instruction Cell Array or RICA, is intended for use in system-on-chip devices and in particular for consumer applications where the RICA fabric can be used to accelerate computationally-intensive parts of software.

"RICA is a major step forward in high performance reconfigurable system on chip technology and is the first time system designers can deliver a combination of very low power coupled with very high performance chips using minimum expertise in hardware design and without requiring large design teams" said Tughrul Arslan, the company's CTO, in a statement.

Arslan, a professor of electronic engineering at Edinburgh university, has retained his academic post while guiding the commercialization at Spiral Gateway of a several technologies developed under him.

RICA is a patented design architecture that is both dynamically reconfigurable and software programmable but it has been designed specifically to meet the needs of data-intensive mobile applications. The processing data-path is a reconfigurable array of heterogeneous instruction cells that are configured directly from software, the company said. The coarse grain of the instruction cells provide much lower power consumption than FPGAs, and can execute any code in a similar manner to conventional processors, Spiral Gateway said.

As a result RICA achieves the performance of conventionally designed hardware at an order of magnitude lower power consumption than a design implemented in an FPGA, the company claimed. RICA also achieves the same functionality as software-programmed RISC, DSP and VLIW processors at lower power consumption, Spiral Gateway added.

Most significantly Spiral Gateway claims that with only an open source C compiler any existing or new C code can load straight onto the fabric. And theoretically this can be done post-production to upgrade an SOC device that has already been sold and is in the field.

The RICA fabric approach appears to have similarities to the D-Fabrix approach of Elixent Ltd. (Bristol, England), a spin-off from Hewlett Packard Laboratories. Elixent recently received substantial backing from two lead customers, Toshiba and Matsushita, and has ported its array to multiple 130-nanometer manufacturing processes (see May 17 story).

The RICA array of reconfigurable heterogeneous instruction cells is composed into cores. According to information at Spiral Gateway's website three cores are available so far, a general-purpose core, and two cores targeted specifically at multimedia and communications respectively.

Specific cores are not restricted to a particular domain, and can run any code, however power consumption will be lowest if used for their targeted application, the website said. Three cores are under development targeting networking applications, speech synthesis, and software defined radio, the website said.

"This [RICA] is the latest step of a strategy that began with the launch of an ultra low power ASIC library at the end of 2004," said Matthew Lawrenson, Spiral Gateway's chief executive officer, in a statement. "Now the drive is to merge the two technologies maintaining the software programmability, but with the ability to adjust the coarseness of the fabric, giving a designer the ability to trade-off flexibility with power consumption and performance. While the technology is already lower-power than its alternatives the whole power consumption curve can be shifted downwards even further with the inclusion of our algorithmic techniques," he added.

Besides a low-power ASIC library, Spiral Gateway has algorithmic tools for reducing power consumption in data-intensive circuit blocks by optimizing configurations to reduce switching capacitance, switching activity and to minimize memory transitions.

The ASIC library contains blocks of a complexity ranging from simple math units up to FIR filters, and MPEG blocks, Lawrenson said. "We use algorithmic techniques to reduce power consumption by 30 to 50 percent," said Lawrenson. "We use circuit analysis to look at the blocks and minimize the switching activity, to reduce data transfers. We have about 40 techniques we use," he added.

"A second development we have is to add reconfigurable elements to blocks. So, for example, a Viterbi codec can be reconfigured to work across multiple applications."

Lawrenson said that RICA is the third-arm of the company's strategy where a generic reconfigurable fabric can be programmed directly with C. He added that the technology had not yet been taken to silicon. "We are putting together a project with lead customers to get some test chips made," Lawrenson added.

Spiral Gateway was operated as the IP Shells project from within the University of Edinburgh before being spinning out as a separate company as Spiral Gateway in September 2004.