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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Silicon Hive announces two new Avispa processors
June 22, 2005 -- Silicon Hive has announced two new cores in the award-winning Avispa family. The new cores are the Avispa CH1 processor, a very high performance, programmable inner-receiver processor optimised for OFDM systems; and the Avispa IM1 processor, a fairly-general, high-performance, low-cost VLIW processor ideal for printing and imaging applications. Both cores are available immediately for licensing. The core's datasheets are available for downloading below:
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