LSI Logic Maximizes Nanometer SoC Integration With Enhanced Design Optimization Methodology
- Core in I/O(TM) methodology offers ASIC/SoC designers optimal use of both core and I/O area for logic design through 'smart management' of I/O and core logic placement
- As compared to standard I/O placement schemes, Core in I/O methodology provides an improved design experience with greater design flexibility and the industry's most aggressive die size design solutions
MILPITAS, Calif., June 28 /PRNewswire-FirstCall/ -- Taking the next evolutionary step in ASIC/SoC co-design technology, LSI Logic Corporation (NYSE: LSI) today introduced Core in I/O(TM) methodology, which provides flexible and optimized I/O placement in Platform ASIC and cell-based ASIC/SoC design by allowing core logic to be placed in the I/O regions.
Following the company's Pad on I/O(TM) and flxI/O(TM) innovations, which allow for the placement of bond pads on top of active circuits in wirebond, and area arrayed signals in flip chip designs respectively, the Core in I/O methodology delivers smart management of I/O assignment by unlocking the I/O ring to extend density advantages offered by these former technologies to optimize silicon area. Designers can benefit by having maximum silicon area to place gates, memory and LSI Logic CoreWare(R) intellectual property (IP) on-chip, resulting in the densest ASIC/SoC design solutions available today. The proprietary technique challenges conventional wisdom of I/O or core-limited design constraints.
"The introduction of the Core in I/O methodology is an industry first for nanometer SoC designs. LSI Logic's co-design technology provides IC designers with the industry's most cost-effective, densest design solutions that ensure optimal use of the silicon design area that's available today," said Stan Mihelcic, director of Advanced Packaging and I/O Technology, Technology Marketing, LSI Logic. "LSI Logic has created yet another innovative technology to allow SoC designers to take full advantage of the integration capabilities of Gflx(TM) and G90(TM) Platform ASIC and cell-based ASIC offerings."
Core in I/O methodology is a proprietary co-design technology based around the company's popular FlexStream(R) and RapidWorx(R) design systems. The scheme includes analysis of physical, electrical, and interconnect constraints for I/O and package connection, enabling floor planning flexibility so designers can reduce routing and placement congestion. Reduced interconnect between core and I/O circuitry can also be realized, improving overall electrical performance. The improved floor planning flexibility and design approach allows for a better design experience and more optimal, efficient design solutions.
Core in I/O methodology encompasses a methodology independent of I/O aspect ratios, enabling flexibility in the use of multiple I/O architectures and libraries. Since there is no compromise to silicon size, IC and CoreWare IP designers have more choices available to them.
Core in I/O technology has been optimized for low cost wirebond packaging solutions typically used in consumer, storage and office automation markets where cost effective ASIC/SoC solutions are required. Core in I/O technology used in conjunction with LSI Logic's revolutionary Pad on I/O technology can provide significant reductions in die size when compared to conventional chip design solutions.
Core in I/O technology is available today for Gflx and G90 cell-based ASIC and Platform ASIC design platforms.
About LSI Logic Corporation
LSI Logic Corporation focuses on the design and production of high-performance semiconductors for Consumer, Communications and Storage applications that access, interconnect and store data, voice and video. LSI Logic engineers incorporate reusable, industry-standard intellectual property building blocks that serve as the heart of leading-edge systems. LSI Logic serves its global OEM, channel and distribution customers with cell-based ASICs, Platform ASICs and standard products, host bus adapters, RAID controllers and software. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035. http://www.lsilogic.com .
SOURCE LSI Logic Corporation
"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Statements in this press release regarding LSI Logic's business which are not historical facts are "forward-looking statements" that involve risks and uncertainties. For a discussion of such risks and uncertainties, which could cause actual results to differ from those contained in the forward-looking statements, see "Risk Factors" in the Company's Annual Report or Form 10-K for the most recently ended fiscal year.
|
Related News
- Enhanced RapidWorx(TM) Design Kit From LSI Logic Accelerates Time to Revenue for SoC Designs
- Dolphin Integration pushes SoC optimization to the next level with all risks managed
- Dolphin Integration's live webinar on Power, Performance and Area optimization during SoC physical implementation
- Logic design optimization takes a quantum leap with Dolphin Integration's standard cell library enriched with pulsed latches
- LSI Logic First to Integrate Dual XFI SerDes Into 10G Ethernet SoC Design
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |