ARCHITECTURES: USB 2.0 climbs aboard silicon

The architecture of the USB protocol lends itself to at least two answers to this query. The data rate in USB is not so fast that a dedicated supercomputer is needed for the protocol stack. In fact, it can execute on a fast 8051-type 8-bit MCU if necessary. Or it can run, with a little careful planning, as a task on an ARM7-class CPU core. These two approaches are illustrated by recent product announcements. Today, ChipX will unveil a 130-nanometer family of structured ASICs with the key blocks of a USB 2.0 On-the-Go core diffused into the base wafer. Last week, Philips Semiconductors announced a family of ARM7-based MCUs with full-speed USB 2.0 target controller capability built in.

The integration strategy for the ChipX family is based on what the company calls the "side chip phenomenon." Increasingly, said vice president of marketing Elie Massabki, designers are partnering a system-level ASIC with a small structured ASIC or FGPA. The major functional blocks of the system — those that have well-defined functions and aren't subject to last-minute changes — go in the SoC, while the stuff that changes from market to market or hour to hour goes in the side chip.

Added functionality
Massabki said a ChipX structured ASIC with built-in USB On-the-Go could replace a discrete USB controller on the board, but add all the functionality of a moderate-size ASIC — from 140,000 to almost 2 million gates, in this case. And, as in the case of the discrete controller, the ChipX devices come with USB compliance certification, relieving the SoC designers of one major headache.

The fast and signal-sensitive parts of the USB interface are diffused onto the base wafer, while the protocol controller state machine and 8051 are synthesized into the structured-ASIC fabric. This gives users the flexibility to execute the software portions of the protocol stack in the 8051, in another type of processor or remotely on the SoC, as they wish. The 6000-family architecture in which the new devices reside provides ample on-chip memory for the buffers and scratchpad necessary to either approach.

A quite different idea from Philips is based not on a dedicated hardware controller and an 8051, but on an ARM7. The company's new LPC214x family consists of ARM7 microcontrollers intended for consumer and industrial applications that require USB connectivity, but that can serve as the system-level chip in the design without an additional ASIC.

In the Philips architecture, the heavy lifting for the USB protocol is done in the ARM CPU. Some subtle but very important hardware additions have been made to make sure that this works, while leaving the bulk of the ARM's cycles available for applications. "CPU loading by the USB interface gets very high if you generate an interrupt on every packet and make the CPU sort through the data and move it around," said Ata Khan, Philips' director of product innovation. "To alleviate this problem, we have designed a USB-aware DMA controller that is able to identify the content of a USB packet and move it to the right endpoints in memory appropriately, without processor intervention."

The approach was so efficient that Philips found that with the addition of only a little bit more buffer RAM, the devices could support the full USB-specified 32 endpoints and still have room to handle 1,023-byte isochronous packets.

The chip introduces several other efficiencies into the ARM MCU architecture as well. There are two independent nominal-10-bit A/D converters that can, if desired, be synchronized to perform simultaneous current and voltage measurements for power-factor computation. The converters are provided with an output buffer per channel, slashing the number of interrupts they generate in multichannel operation. The chips also offer a full nominal-10-bit D/A, instead of the usual PWM outputs, reducing noise, outside component count and, again, CPU load.

Traditionally, MCU users have implemented custom binary interfaces by simply directly setting or clearing pins on the MCU. But in the ARM architecture, the registers for these pins migrated out to the low-speed ARM Peripheral Bus (APB). That introduced a latency of so many cycles that a 60-MHz ARM could only toggle its I/O pins at under 4 MHz, Khan said. Philips moved the registers from the APB to the CPU local bus. This eliminates so many latency cycles that the chip can toggle its I/O pins at 15 MHz under software control.

All these ideas lead to a careful allocation of the most precious commodity in 32-bit MCUs: processor latency. It means that full-speed USB, streaming data conversion, real-time device control and meaningful computation can all happen without adding processors or giving up on the internal USB controller and buying the discrete USB chip.