Shift to 65 nm has its costs

Indeed, there are no wrenching materials changes as IC designs migrate to 65 nm: A switch to nickel silicide from cobalt is the one big adjustment. But design goals will still face off against technological realities on a host of fronts, process experts say. Here, in order, are the challenges they identified as the Top 10 for the 65-nm node.

1 The cost increases that result from rising design complexity may delay the shift to 65 nm, Pinto said. That transition might otherwise have been expeditious, given that lithography tools and materials won't change appreciably from those used at the 90-nm node.

While engineers tend to associate a new technology node primarily with performance gains, the attraction of the 65-nm node is that it brings density advantages, with 10 million transistors crammed into each square millimeter. That's a mixed blessing. "Integration is still a good thing," Pinto said, "but it takes a huge amount of money, and some people may stay on the sidelines.

. . . Consumer devices today have a lot more functionality, and with 65 nm, the cost per transistor is going down. Will those kinds of applications take advantage of the better cost per transistor? We'll have to see."

But one certainty, Pinto said, is that "demand from China is only going to grow — and 65 nm is absolutely ideal for consumer chips aimed at growing markets."

Pinto said his biggest worry is that EDA tool costs are growing quickly for 65-nm design teams.

To keep costs within reason, said Srini Raghvendra, senior director of design-for-manufacturing (DFM) at Synopsys Inc., process technology must be standardized so that intellectual-property reuse can be brought to bear. Design productivity, measured in terms of gates per engineering workday, must improve fourfold at 65 nm over the 130-nm node, Raghvendra said.

2Controlling power can add to design complexity, making it more challenging to keep costs in check. All of those added millions of transistors, with streaming video running on a battery-powered device, for example, devour power. Addressing the problem requires architectural, system-level decisions, said Eric Filseth, a marketing manager at Cadence Design Systems Inc.

"The easy stuff people already do — things like high- and low-leakage cells, clock gating and multiple threshold voltages. The next stage is multiple power domains," Filseth said.

Power is determined by the voltage squared. So, if a design team can drop a portion of the chip from 1.2 volts to 1 V, for example, that 200-mV difference can provide a sharp improvement in overall power consumption.

"Multiple power domains are a major step for many customers at 65 nm," Filseth said. "The tools need to understand MPDs. Timing needs to understand two different voltages, and the tools have to insert new kinds of structures, such as special level shifters."

3Hardware-software co-design becomes more crucial at 65 nm. Software creation claims the greatest fraction of the overall chip development budget and can easily delay time-to-market if mishandled.

Teams must start on software creation at the same time that register-transfer-level design commences, said Tohru Furuyama, general manager of research and development at Toshiba Corp.'s system-on-chip engineering center in Kawasaki, Japan.

Japanese companies have shown some leadership in hardware-software co-development. "With good C-based models for the circuits, we can start software development before the silicon is available," Furuyama said in an interview at the VLSI symposium.

Toshiba has forged an alliance with CoWare Inc. to develop the methodology, while NEC Corp. is creating its co-development tools in-house.

With65-nm mask sets estimated to cost $3 million, more companies are opting to develop simulation models "so that applications code can be developed and tested before a mask set is created," said Rich Curtin, senior vice president of business development at Tharas Systems Inc., a Silicon Valley startup working on hardware/software simulation tools that counts Toshiba as a customer.

4Tighter restrictions and more rules are a given for design teams working at 65 nm. Polysilicon gate orientations must be maintained more strictly in a design's horizontal or vertical planes. That's a boost for design-for-manufacturing because it keeps optical proximity correction (OPC) from exploding.

Dave Bearden, manager of network MPU design at Freescale Semiconductor Inc., said Freescale teams working on 65-nm designs have "a more restrained poly environment on how the transistor's gate gets laid out. For a NAND gate or a latch, we put down a poly line and have more-restrictive rules on the adjacent poly. There are restrictions on doing V and H [vertical and horizontal] and 45-degree lines on the same die. The idea is to keep them all parallel or all perpendicular."

By limiting options for how IP is characterized at the back end, modeling and fab costs can be controlled more easily, said Jon Cheek, manager of 65-nm design and integration at Freescale. A requirement for two back ends can add to reticle costs and complicate communications between the designers and the IP providers.

The more-restrictive rules "help us with our Spice models and result in a better representation of the world we can give the designers. We can't make a million models and expect to squeeze more juice [performance] from the designs," Cheek said.

For the 65-nm node, IBM's microelectronics operation added DFM rules to create patterns that are more regular and tuned, said Lisa Su, vice president for technology development and alliances at IBM's Systems and Technology Group.

"We made some tough decisions to add design rules at the 65-nm node, aligning the gates in a single direction. That's painful for the designers, but it is important for line-width control," she said.

Designers now are limited to a certain number of pitches, with regular spacing of the gates.

"When we first did this, we thought it would take away from performance and reduce density, but [those reductions] turned out to be not nearly as much as we originally thought," Su said. "The designers just have to get used to [the need for gate alignment] and be told up-front. It can be a powerful tool. From a technology standpoint, I love it. But we had to get the design infrastructure ready three years ago."

5Traveling the learning curve for strained silicon becomes more critical, given the potential to rein in drive current. William Holt, vice president of Intel Corp. and general manager of its Technology and Manufacturing Group (Hillsboro, Ore.), said Intel's "second complete revision" of strained silicon at the 65-nm node provided a 15 to 20 percent improvement in drive current compared with the 90-nm node.

"At 65 nm, it's still all about the transistor. We were able to learn quite a bit more about strained silicon. As a result, we can adjust our Ion/Ioff curves so we can improve the drive current without a corresponding increase in leakage. That allows us to move the curve to the right, or we can move down and take a fourfold reduction in leakage."

Intel was able to improve the channel length somewhat at 65 nm to get improvements in performance, but "the vast majority of the improvement comes from strained silicon," Holt said.

6Process variability becomes a much larger factor as dopant distributions become more difficult to control and gate oxide thicknesses shrink to only a few molecules. At a heavily attended panel discussion on variability at the VLSI Symposium, Hisashige Ando, a top microprocessor design manager at Fujitsu Ltd., outlined a series of coping strategies for variability. They ranged from complementary static gates on the logic to redundant SRAM rows in the caches.

Overall, however, "I don't think variability is such a huge problem," Ando concluded. "Life is not so bad."

Variability is particularly hard on memory arrays, process experts said. Dopant fluctuations in the channel and in the halo regions of the source and drain, line edge roughness, and other difficult-to-control sources of variability come to the fore at 65 nm.

7With on-chip SRAM and other embedded memories consuming 70 percent or more of a design's transistors, the difficulty of maintaining a decent signal-to-noise margin increases substantially at the 65-nm node.

Furuyama said Toshiba and many other companies are considering using multiple power supplies, with a slightly higher operating voltage and threshold voltage for the SRAM array, to suppress leakage and maintain stability in the SRAM bit cells. Another approach is to use eight transistors, instead of six, for each SRAM bit.

Seshadri Subbanna, director of IBM's research activities at Albany Nanotech, said variability does require adjustments in the SRAM arrays. IBM will use about 200 mV more current for the arrays than for logic and will use larger SRAM cells, he said. "With so much of the die being used for memory, keeping the performance of the SRAM array up is critical," Subbanna said. "So we will go with bigger cells."

8Signal integrity becomes more problematic as wires are spaced closer together, said David Pan, a physical design researcher and professor at the University of Texas at Austin. "At 65 nm, the conventional placement algorithms often don't work right. A lot of design closure problems are caused by interconnect issues, particularly by poor placement of the longer wires."

Intel's Holt said his group worked to improve the etch stop to get a net capacitance improvement at the back end, adding that "we can do more along that line."

Also, for Intel's 65-nm technology, the pitch can vary on all layers to optimize cost and performance, Holt said.

9A $3 million mask set is a daunting barrier to many design teams pondering the shift to 65-nm design rules. Still, the mask set remains a relatively small cost element of projects that can require $40 million to $100 million in total expenditures.

Applied Materials is working on improved mask-writing tools, Pinto said. "Mask write time goes up as OPC is used on more layers. And it is not all 4x [reductions from the mask to the wafer]. Some features are written at 1x or 2x, and that's challenging.

"The mask shops will tell you that if the mask write time is more than 24 hours, they are dead in terms of costs. And with such long write times, they can't meet the time-to-market specs."

10Design-for-test, built-in self-test, compression and other techniques are requisite for keeping 65-nm costs under control . "Process variations can result in more chips being out of spec," said Raghvendra of Synopsys.

To weed out the chips that don't hit targets, companies are forced to do more at-speed testing. Design and test engineers must work together to develop tests "that are as inexpensive as possible," Raghvendra said, "and that impacts the design methodology."