English
Structured ASICs deserve serious attention at 90 nm
Four years after ASIC vendors introduced their first structured-ASIC devices in response to FPGA vendors eating up their market share, the structured-ASIC market has yet to become a popular choice for logic designs.
But analysts say that the structured-ASIC market is a viable business today and may exceed $1 billion by 2008, as designers add up the cost of 90-nm ASIC design and run up against the hard limitations of FPGAs.
Analysts and structured-ASIC vendors put up good arguments about why you should at least consider structured fabric for your next IC-design project. But you should consider a number of variables—both technical and business—when evaluating FPGAs, structured ASICs, and cell-based ASICs.
Companies market structured ASICs as the midvolume, midprice missing link between fast-turnaround, reprogrammable but low-volume FPGAs and high-cost, high-volume, hard-to-design cell-based ASICs.
A structured device resembles a gate array on steroids. Like gate arrays, structured ASICs have a limited number of designable layers (usually one to six), a low tool and NRE cost, and a turnaround time ranging from days to months. As with gate arrays, silicon vendors have taken care of most of the nasty physical-design effects with prerouted and pretested layers. In most devices, they've also predesigned the clock tree. But structured-ASIC devices offer much larger designable gate counts and much more on-chip memory than gate arrays.
Click here to read more ...
Related News
- eASIC rolls 90-nm structured ASIC line
- Platform ASICs a natural fit at 90 nm, say DAC panelists
- Fujitsu hurries 90-nm structured ASIC
- US Government to Fund Expansion of IP Ecosystem for SkyWater's 90 nm Rad-Hard Platform
- SkyWater Receives Funding from DOD, Partners with Google to Facilitate Open Source Design for its new 90 nm Technology Offering
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |