English
Genesys Logic First to Market with PCI Express PIPE PHY Chip
July 14, 2005 -- San Jose -- Genesys Logic, Inc. (GLI) the high speed I/O communications specialist, today announced full production and availability of its PCI Express GigaCourier™ GL9711 integrated circuit (IC). The device provides PCB developers, for the first time, with an access speed of 2.5Gbps and a 125MHz/16-bit or 250MHz/8-bit PIPE interface.
“The availability of our latest version of the GigaCourier, GL9711 1-lane PIPE PHY chips, allows FPGA designers to take full advantage of the high-speed PCI Express standard,” said Jerry Chen, Director of Technology at Genesys Logic. “The GL9711 is the first PCI Express 1-lane PIPE PHY discrete chip in the industry implemented in a 0.18ìm standard digital CMOS process and is already supported by key core logic IP partners in the US and Japan.”
This first discrete solution to the PCI express standard is available immediately and priced around $5.00 in quantities of 25,000.
GL9711 and the soon-to-be-released GL9714 4-lane version, fully comply with both the PCI ExpressTM Base Specification Revision 1.0a and the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel. The GL9714, available in Q4, 2005 will be a four-lane transceiver, to be designed in as either 8/16/32 lanes configuration to meet the demand of various bandwidth specifications for networking, graphics, storage, and many other high-speed applications.
“The availability of our latest version of the GigaCourier, GL9711 1-lane PIPE PHY chips, allows FPGA designers to take full advantage of the high-speed PCI Express standard,” said Jerry Chen, Director of Technology at Genesys Logic. “The GL9711 is the first PCI Express 1-lane PIPE PHY discrete chip in the industry implemented in a 0.18ìm standard digital CMOS process and is already supported by key core logic IP partners in the US and Japan.”
This first discrete solution to the PCI express standard is available immediately and priced around $5.00 in quantities of 25,000.
GL9711 and the soon-to-be-released GL9714 4-lane version, fully comply with both the PCI ExpressTM Base Specification Revision 1.0a and the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel. The GL9714, available in Q4, 2005 will be a four-lane transceiver, to be designed in as either 8/16/32 lanes configuration to meet the demand of various bandwidth specifications for networking, graphics, storage, and many other high-speed applications.
|
||||||
Related News
- Genesys Logic First to Market with PCI Express 4-lane 10Gbps PIPE PHY Chips
- Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP
- Altera and Genesys Logic Deliver PCI-SIG-Compliant x4 PCI Express Solution
- Programmable PCI Express Solution Announced by Lattice Semiconductor, Genesys Logic and Northwest Logic
- Genesys Logic Introduces PCI Express and GigaSata Serial ATA Products at IDF Spring 2005
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |