NextIO Selects Denali PureSpec for PCI Express Design Verification
PALO ALTO, Calif., July 22, 2005 -- Denali and NextIO, Inc., a chip developer for enterprise-class computer servers, today announced an agreement that provides NextIO with Denali's PureSpec™ verification intellectual property (IP) for functional verification of the PCI Express interface of its enterprise server chips.
NextIO engineers are using PureSpec at the pre-silicon stage of design to simulate interactions through the PCI Express interface in order to verify the correct and optimal operation of the chip's design.
"Denali's PureSpec is the most trusted solution for verifying PCI Express designs," notes Chris Pettey, CTO of NextIO. "We have a veteran design team with extensive experience in the server market and they asked for Denali's PureSpec. In addition to its superior technology for exposing design issues, the widespread use of PureSpec gives us the added confidence in verifying interoperability with other PCI Express designs."
Denali's PureSpec verification IP includes a configurable bus functional model (BFM) integrated with thousands of assertions that enable NextIO to verify its PCI Express interface for compliance with the specification and interoperability with other PCI Express devices. Used by more than 60 companies worldwide, PureSpec is the most widely used verification IP product for simulating and verifying PCI Express design interfaces. "Interface verification is playing an increasingly critical role in advanced chip development flows such as NextIO's," adds David Lin, Denali's vice president of Product Marketing at Denali. "PureSpec is a well-architected product that reduces risk and delivers real verification productivity. It's nice to see that we hit the mark with a leading-edge design effort, and we are pleased to be a part of NextIO's design verification flow."
About PureSpec
PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers -- physical, data link, transaction -- of the PCI Express specification are modeled and can be simulated concurrently or independently. It provides seamless integrations to all popular electronic design automation (EDA) tools and verification languages. PureSpec is available now for customer evaluation at: www.denali.com/purespec.
About NextIO
NextIO, Inc. is a developer of next-generation chips for enterprise-class computer servers. Led by a team of semiconductor veterans, NextIO is based in Austin, Texas and is a privately held company funded by Crescendo Ventures, Adams Capital Management, JK&B Capital, VentureTech Alliance (TSMC) and Dell.
About Denali
Denali Software Inc. is the world's leading provider of EDA tools and Intellectual Property (IP) solutions for chip interface design, integration and verification. Its Databahn™ Design IP products offer fully configurable design cores for complex interfaces such as Serial ATA and DDR-based memory systems. Denali's PureSpec™ Verification IP product supports all complex interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, visit Denali at http://www.denali.com. Telephone: (650) 461-7200.
The Denali logo, Denali, and Databahn, PureSpec, MMAV and SOMA are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.
|
Related News
- NextIO Adopts Denali's Verification IP for New PCI Express Expansion and I/O Virtualization Module for Blade Systems
- Denali Announces Complete Bundle of I/O Virtualization Technology Solution With PureSpec PCI Express Verification IP
- Sony Selects Denali PureSpec PCI Express Verification IP for SxS PRO Memory Card
- ConnectX InfiniBand Adapters and 10Gb Ethernet NICs Designed for PCI Express 2.0 Technology with Denali PureSpec Verification IP
- ASIC Architect, Inc. Selects Denali PureSpec for PCI Express Interface Verification
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |