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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Faraday Announces Ultra-High-Density miniIP Silicon IP Platform for UMC 0.18um Process
25% of die size reduction and significant power-saving features make 0.18µm process appealing to cost sensitive applications
HSINCHU, Taiwan and SUNNYVALE, California, – August 2, 2005 -- Faraday Technology Corporation (TAIEX: 3035), a leading ASIC and IP provider, today announced miniIP platform, the first comprehensive 0.18µm IP portfolio designed specifically for cost-sensitive and high time-to-market pressure consumer devices.
With all the hypes, the 0.13µm technology still isn't a viable option to many cost sensitive consumer devices, due to the high mask cost, long turn-around time and high design risks. After comparison, many IC design houses find it makes more sense to improve the efficiency of the matured low-cost 0.18µm process technology for their next generation chips, instead of resorting to 0.13µm technology.
“Faraday's miniIP platform is a complete IP portfolio optimized for chip designers to achieve first silicon cut success, and fast time-to-market,” said Hsin Wang, Associate Vice President of Faraday. “By delivering 25% or more reduction in die size and power dissipation, the miniIP platform promises our customers significant cost advantages and much longer product battery life, two of the most important features consumers care about”
Faraday's miniIP platform includes:
miniLib™ : High-density cell library with 20~30% reduction in core logic area and power consumption when compared with other standard cell libraries; suitable for devices operating at 1.35V ~ 1.98V.
miniIO™ : High-density general purpose I/Os with 40% reduction in the I/O area over the conventional ones.
POC™: Pad-Over-Circuit technology which can reduce 5~10% of overall chip cost by moving the bonding pads above the I/O cells.
miniPLL™ : Essential component PLL completely integrated into the I/O region without taking any core area.
miniROM™ Compiler : High-density diffusion programmable ROM generator which can gain 25% area reduction on the same configuration generated by conventional compilers.
Availability:
The complete set of miniIP portfolio has been silicon proven at UMC 0.18µm process and is available now. For more information, please contact Faraday sales or regional sales reps.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, and PHYs/Controllers for USB 2.0, Ethernet, Serial ATA and PCI Express. With more than 500 employees and 2004 revenue of US$159 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan , Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit: http://www.faraday-tech.com
HSINCHU, Taiwan and SUNNYVALE, California, – August 2, 2005 -- Faraday Technology Corporation (TAIEX: 3035), a leading ASIC and IP provider, today announced miniIP platform, the first comprehensive 0.18µm IP portfolio designed specifically for cost-sensitive and high time-to-market pressure consumer devices.
With all the hypes, the 0.13µm technology still isn't a viable option to many cost sensitive consumer devices, due to the high mask cost, long turn-around time and high design risks. After comparison, many IC design houses find it makes more sense to improve the efficiency of the matured low-cost 0.18µm process technology for their next generation chips, instead of resorting to 0.13µm technology.
“Faraday's miniIP platform is a complete IP portfolio optimized for chip designers to achieve first silicon cut success, and fast time-to-market,” said Hsin Wang, Associate Vice President of Faraday. “By delivering 25% or more reduction in die size and power dissipation, the miniIP platform promises our customers significant cost advantages and much longer product battery life, two of the most important features consumers care about”
Faraday's miniIP platform includes:
miniLib™ : High-density cell library with 20~30% reduction in core logic area and power consumption when compared with other standard cell libraries; suitable for devices operating at 1.35V ~ 1.98V.
miniIO™ : High-density general purpose I/Os with 40% reduction in the I/O area over the conventional ones.
POC™: Pad-Over-Circuit technology which can reduce 5~10% of overall chip cost by moving the bonding pads above the I/O cells.
miniPLL™ : Essential component PLL completely integrated into the I/O region without taking any core area.
miniROM™ Compiler : High-density diffusion programmable ROM generator which can gain 25% area reduction on the same configuration generated by conventional compilers.
Availability:
The complete set of miniIP portfolio has been silicon proven at UMC 0.18µm process and is available now. For more information, please contact Faraday sales or regional sales reps.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, and PHYs/Controllers for USB 2.0, Ethernet, Serial ATA and PCI Express. With more than 500 employees and 2004 revenue of US$159 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan , Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit: http://www.faraday-tech.com
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