Open Core Protocol International Partnership Releases OCP SystemC Channel 2.1.1 and Methodology White Paper
Version 2.1.1 improves module interoperability by unifying the way time is modeled in transaction level 1. Some TL1 API functions have also been redesigned to ensure interoperability, and new timing interfaces have been added to the TL1 channel for automating the setting of module timing parameters. Improved support for OCP thread busy signaling has also been added to TL1. In addition, a wrapper channel, which includes a clock input port is provided for TL1 to make the channel easier to use with EDA tools. Single-request, multiple-data OCP transactions have been implemented for TL2.
The methodology package outlines the use of the OCP TLM in the same flow with the OSCI TLM, and introduces a newly defined modeling abstraction level, Architects View, using OCP TL2 or TL3 for interface modeling. The methodology package has extensive examples for modeling in different abstraction levels, and for making models of different abstractions interoperable.
Work on the compliance models was completed by the OCP-IP System Level Design Working Group including representatives from: CoWare, Nokia, Sonics, and TI.
“Our System Level Design Working Group is full of the best and brightest engineers in the world from leading companies working on Transaction Level Models,” said Ian Mackintosh, president OCP-IP. “We are particularly proud of the quality and ongoing evolution of the modeling standard we have pioneered.”
For more information please visit the OCP-IP website at www.ocpip.org.
About OCP-IP
|
Related News
- Open Core Protocol International Partnership Releases OCP SystemC Channel Version 2.1.3
- Open Core Protocol International Partnership Releases OCP SystemC Channel Version 2.1.2
- Open Core Protocol International Partnership Releases OCP SystemC Channel Version 2.2
- Jasper Design Automation Joins Open Core Protocol International Partnership (OCP-IP)
- The Open SystemC Initiative and the Open Core Protocol International Partnership Join Forces to Target TLM Layer Standardization
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |