PLDApplications Solution Passes PCI Express Compliance Testing with Rambus PHY

Endpoint controller solution now on PCI-SIG Integrators List

SAN JOSE, Calif. – August 23, 2005 – PLDApplications (PLDA), the world's largest PCI IP Core vendor, today announced that their PCI Express* Endpoint controller, which incorporates Rambus’s PCI Express PHY, has successfully completed vigorous PCI-SIG compliance and interoperability testing. The PLDA PCI Express IP solution passed all the test criteria set forth at the PCI-SIG Compliance Workshops including protocol, electrical, and configuration tests.   

“PLDA has a compelling solution that is now tested and proven and, coupled with our PHY offering, meets the growing demand of PCI Express applications,” said Jean-Marc Patenaude, director of marketing for logic interface products at Rambus.  “Working with PLDA on this accomplishment is rewarding as it furthers our position as the most broadly interoperable PHY solution available.”

PLDA's PCI Express IP Core is available as a Root Port, an Endpoint, or in a dual mode RP / EP version and supports x1, x4, and x8 lane configurations. The Core supports all required PCI Express protocol features of all three layers and implements many non-required features, such as End to End Cyclic Redundancy Checks (ECRC), Advanced Error Reporting (AER), hotplug support, variable payload size, and a choice of 1 – 8 virtual channels. For more information regarding PLDA's growing line of PCI Express IP Cores and Prototyping Boards, please visit www.plda.com.

"Not only does today's announcement solidify PLDA's position as one of the first, and now multiple-listed, members of the PCI Express integrators list," said Arnaud Schleich, Vice President of PLDA, "but it also expands our range of solutions by proving interoperability with Rambus's PCI Express PHY, one of the most popular PHYs on the market today."

Rambus PCI Express PHYs are complete serial communication cells optimized for implementing the physical layer of the PCI Express standard.  The silicon-proven serial interfaces feature point-to-point, full duplex signaling and support up to a 3.2Gbps data rate.  The Rambus PCI Express PHY design is available on multiple foundry and captive processes at process nodes ranging from 180nm to 65nm.  The PHYs are in production in high-volume applications such as PC graphics, chipsets, switch and bridge chips, and supported by a comprehensive suite of digital controllers and support services to provide chip developers with a complete system solution. 

About PLD Applications

PLDA, the world's largest PCI IP Module vendor (Gartner, 2005), designs and sells a wide range of ASIC and FPGA interfacing solutions for the PCI and derivative markets (PCI Express, PCI-X, CompactPCI, and PC104/PC104+). The company offers complete solutions to a global market, including IP cores, hardware, software, consulting services, and comprehensive technical support provided directly by the IP designers. For additional information about PLD Applications, please visit http://www.plda.com

Rambus is a registered trademark of Rambus Inc. All other trade names are the service marks, trademarks, or registered trademarks of their respective owners.

*PCI Express is a trademark of PCI-SIG.

PCI-SIG is the special interest group that owns and manages PCI specifications as open industry standards.

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