PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N4P. N5 , N6
Aplus to Provide Low-Power, Low Voltage (1.8V) Operation EEPROM Macro Solution at UMC
Update: Aplus Flash Technology is no more in business
SAN JOSE, Calif.--Aug. 29, 2005--Aplus Flash Technology, a privately-held, fabless provider of nonvolatile memory (NVM) products and customized NVM IP, today announced that it has signed an agreement whereby it will develop EEPROM Semiconductor Intellectual Property (IP) for UMC's 0.35um EEPROM process technology. This effort will provide UMC's foundry customers with access to Aplus' high-performance EEPROM IP and comprehensive support services when designing their IC and System-On-Chip (SoC) products.
The Aplus EEPROM memory macro is being built to target applications requiring non-volatile memory storage for program or data, offering flexible page write or in-system byte write/erase functionality with high program/erase cycles. It is designed to operate over a temperature range of -35 degrees C to 85 degrees C. The macro block is also designed to be customized in order to meet various customer requirements for low-power, low-voltage, and high-performance capabilities. This is intended to allow customers the flexibility to utilize the memory to target different specifications for applications such as smart card, SIM card, RFID, security ICs, ID, and other products that require data storage to a byte erasable/programmable level.Ken Liou, Director of the IP and Design Support division at UMC, said, "Non-volatile memory plays an important role in a variety of semiconductor industry applications. As such, we are pleased to have Aplus, a valuable IP provider of non-volatile memory solutions, port its non-volatile EEPROM IP to our process technology. We look forward to making their IP solutions available to our customers designing for applications that benefit from EEPROM technology."
"Aplus' commitment is to provide foundry flexibility for our NVM IP customers. Our agreement with UMC will make Aplus' leading EEPROM IP more widely available to customers targeting UMC's process technologies," said Peter Lee, CEO of Aplus. "As SoCs grow increasingly complex and the need for non-volatile memory increases, the IP offerings from Aplus ported to UMC's process technology should provide great value in accelerating our customers' time-to-market and reducing their design cycle and risk while enhancing their products' functionality and performance."
The EEPROM Semiconductor IP is targeted to be available in Q4 of 2005.
About Aplus Flash Technology (www.aplusflash.com):
Aplus Flash Technology is a fabless IC company offering non-volatile memory IP and memory products. Its line of NVM IP includes ROM, OTP, NTP, EEPROM, FLASH+EEPROM and FLASH, and can be embedded into a variety of communications, computing and consumer applications. Aplus offers both standard IP blocks as well as customized ASIC designs. In addition to its IP Aplus also develops standard memory products. Its IP blocks can be found in applications from smart cards to talking toys to microcontrollers and other IC drivers. Aplus' embedded licensees including leading global semiconductor companies and its foundry connections span worldwide in countries including Taiwan, Korea and China.
Source: Aplus Flash Technology
|
Related News
- Chipidea's New USB PHY Architecture for 1.8V Devices Offers Industry's Lowest Power Consumption for SoC Designers
- MOSCAD Design & Automation Releases Ultra low-power Voltage regulator cell in 55nm
- Shenzhen Integrated Circuit Design Industrial Center Licenses Low-Power Cores from MIPS Technologies
- Actel Expands Processor Ecosystem for Low-Power FPGAs
- ARM, Renesas Technology and Synopsys Define Industry's First Low-Power Verification Methodology
Breaking News
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Most Popular
- DENSO and U.S. Startup Quadric Sign Development License Agreement for AI Semiconductor (NPU)
- Xiphera and Crypto Quantique Announce Partnership for Quantum-Resilient Hardware Trust Engines
- Arm's power play will backfire
- Alchip Announces Successful 2nm Test Chip Tapeout
- Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs
E-mail This Article | Printer-Friendly Page |