Process Detector (For DVFS and monitoring process variation)
SOISIC Announces Semiconductor Industry's First Silicon- Proven 90nm High-Speed Silicon-On-Insulator Design Kit
The design kit consists of multi-Vt standard cell libraries, memory compilers and standard I/Os for manufacturing on Freescale 90-nm SOI process technology. The immediate availability of the SOISIC Design Kit marks the entry of SOI technologies in the mainstream COT market. Other COT announcements are expected to follow.
“Until now, SOI supply was limited to large integrated devices manufacturers (IDMs) with proprietary EDA tools and flows and substantial up-front investment,” said Eduard R. Weichselbaumer, President and CEO of SOISIC. “SOISIC world class IP team has integrated Freescale advanced SOI process technology with best-in-class device and design expertise to make this technology available to the mainstream COT market.”
SOISIC is currently in the third generation of IP development at the 90-nm node. The market requires new devices with increased speed and lower power consumption concurrently. SOISIC Freescale-Soisic90nmSOICOTPR-final.doc
Design Kit will allow designers to fully utilize the benefits of SOI to meet the performance and power consumption benchmarks the industry demands.
This SOI technology demonstrates outstanding speed and power benefits compared with 90nm bulk CMOS processes:
- 30 to 40 percent speed improvement
- Reduction of power consumption by a factor of 2x
- Up to 10 percent area reduction.
This is achieved using SOISIC SOI-specific patented IP, patented characterization methodology and proprietary architectures.
SOI design kit works with Standard EDA tools and flows
The SOISIC Design Kit lets SoC designers design with their industry standard EDA tool flows. No specific tools or retraining of customer engineers is required because all SOI specific effects are handled at the IP level making it fully transparent to the designers.
SOISIC continues to work closely with major EDA tool vendors to enhance their tool capabilities. The full design kit is available today from SOISIC.
About SOISIC:
SOISIC is the world’s leading company in Semiconductor IP for Silicon On Insulator technologies. The Company has worked across the globe in multiple SOI Processes and Multiple nodes from .25µm down to 90nm, both in Ultra Low Power and High Performance. SOISIC has helped some of the world's leading companies begin their SOI Development and to use SOI for low-power applications. www.soisic.com
|
Related News
- SOISIC Achieves First-Time-Right Silicon From 90nm High-Speed Silicon-On-Insulator tape-outs
- Acacia Semiconductor Announces a New Family of Best-in-Class High-Speed 10-bit ADC IPs Silicon Proven in a 130nm Process
- EVE's ZeBu Proven High-Speed Verification Solution for IBM PowerPC 405, 440 SoC Designs
- Rambus India High-Speed I/O Design Team Achieves First Silicon Success; TSMC 90nm PCI Express* 2.5Gbps design fully characterized and compliant to specification
- IC Knowledge's Cost Modeling of Semiconductor Manufacturing Shows Fully Depleted Silicon-on-Insulator Technology to be the Most Cost-effective Approach at the 22nm Node
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |