ARC Cores selects Synopsys high-level design tools for SoC evaluation platform
ARC Cores selects Synopsys high-level design tools for SoC evaluation platform
Edinburgh, Scotland, 23 October 2000 - ARC Cores has signed an agreement with Synopsys, Inc. [NASDAQ:SNPS] to provide a suite of high-level design tools for ARC?s processor evaluation platform. The platform, which is designed to prototype and benchmark devices incorporating the configurable ARC processor, will integrate Synopsys? design software, creating a comprehensive system-on-chip development tool chain.
The ARC evaluation platform combines ARC?s ARChitect tool, key Synopsys products and a Sun Microsystems Ultra? 5 workstation that has been secured to prevent unauthorized use of intellectual property during evaluation. Also included in the platform is ARC?s MetaWare software development tool chain with a C/C++ compiler and debugger, in addition to a VHDL compiler/simulator.
According to Andy Elms, director of worldwide customer support at ARC Cores, ?Inclusion of the Synopsys tools allows users to fully benchmark their proposed system prior to purchasing the ARC microprocessor IP.? He continues, ?Designers require both comprehensive design environments and tools to ensure that their design is optimized for the appropriate system performance metrics. Using Synopsys tools as an integral part of our evaluation platform, designers have access to best-in-class EDA tools to fully prove their concepts - whether sensitive to power consumption, area or speed - before making any firm commitment.?
The ARC evaluation platform incorporates the ARChitect tool for configuring the ARC processor and generating VHDL or Verilog RTL. Output from the ARChitect tool is then passed directly to a comprehensive suite of Synopsys high-level design tools. The suite includes: DC Expert Plus TM leading-edge ASIC synthesis with design-for-test capabilities, DesignWare® IP Library, FPGA Compiler II TM advanced synthesis for multimillion-gate FPGA designs, and Power CompilerTM for push-button power reduction and RTL power estimation.
?By including Synopsys software in the evaluation platform ARC?s customers can evaluate the processor in their preferred environment,? said Laura Horsey, manager, IP partnerships at Synopsys. ?The breadth and comprehensiveness of the Synopsys portfolio is the perfect match for ARC?s configurable processor, allowing designers maximum flexibility to achieve their specific system design goals.?
ARC Cores is a trademark of ARC International (UK) Limited. All other brands or product names are the property of their respective holders.
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