Mentor Graphics and Xilinx Announce New Tool for FPGA Design Reuse

SAN JOSE, Calif., Oct. 24 -- Mentor Graphics Corp. (Nasdaq: MENT) and Xilinx, Inc. (Nasdaq: XLNX - ) announced today FPGA OpenMORE, the first reference-scoring program to assess the reusability of IP in large, multi-million gate FPGA designs. FPGA OpenMORE will enable ASIC designers to easily migrate to FPGA design methodologies. FPGA OpenMORE is based on the widely used Reuse Methodology Manual (RMM, second edition) co-authored by Synopsys and Mentor technical staff, with the FPGA portion of the rules and guidelines based on an addendum authored by Xilinx.

``With the availability of the Xilinx next generation Virtex(TM)-II architecture designed for system-level integration and design tools that are compatible with ASIC design methodologies, it's now possible to employ a similar, if not identical, design reuse strategy for ASICs and FPGAs,'' said Mike Frazier, director of engineering for the IP Solutions Division at Xilinx.

In the past, popular design reuse methods and tools have been used solely for system-on-chip designs implemented in an ASIC. With current deep- submicron technology, an increasing amount of system-level functionality can be included on a large, reprogrammable FPGA. FPGA OpenMORE provides a similar scoring program for ASICs and FPGAs, enabling companies to define a reuse strategy that allows designers to work seamlessly between the two technologies.

``The creation of FPGA OpenMORE with FPGA-specific guidelines is an excellent example of how industry leaders can cooperate to further the advancement of system-level design,'' said Newton Abdalla, vice president of IP at CAST, a third-party IP provider that has evaluated FPGA OpenMORE. ``At CAST, we are starting to create more soft IP for FPGAs and have seen an acceleration of existing ASIC IP customers migrating to larger system-level FPGAs. We found the new FPGA OpenMORE program easy-to-use and understand.''

FPGA OpenMORE will contain many of the rules and guidelines from the second edition RMM that apply to Soft IP. The scoring of IP implemented in FPGAs has been made easy-to-use for IP providers migrating ASIC cores to FPGAs by keeping many of the rules and guidelines similar to ASIC rules and guidelines. In addition, the FPGA OpenMORE will add rules and guidelines that are FPGA-specific and includes 130 rules and guidelines for Soft IP assessment and 13 new rules and guidelines specific to FPGAs.

Pierre Bricaud, director of marketing for the IP Division at Mentor Graphics®, said, ``Over the past year, we've added more measurability criteria to the OpenMORE program to keep step with constant changes in the semiconductor industry. The addition of new measurability guidelines for evaluating Soft IP used in FPGA technologies will offer IP designers the same ease-of-use features as the widely-used OpenMORE assessment tool.''

About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

About Mentor Graphics Corp.

Mentor Graphics Corp. is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $500 million and employs approximately 2,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777. Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

NOTE: Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Virtex and Spartan are registered trademarks of Xilinx, Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.

CONTACT: Debbie Price, Strategic Marketing, Inventra IP of Mentor Graphics Corporation, 408-451-5877, or debbie_price@mentor.com; or Jeremiah Glodoveza of Benjamin Group/BSMG Worldwide, 415-352-2628, ext. 559, or jeremiah@benjamingroup.com, for Mentor Graphics Corporation; or Jim Burnham, Product Marketing, 408-879-4971, or jim.burnham@xilinx.com, or Jennifer Wright, 408-879-7727, or jennifer.wright@xilinx.com, both of Xilinx, Inc.