New Agreement Bridges the Gap Between Conventional Design Flows for DSP and FPGA Systems using ESL Tools
Typically performed by system and software engineers, DSP programming relies on a software-oriented approach. FPGA devices are often programmed using design tools evolved from hardware-centric techniques. The different approaches and levels of abstraction make it difficult to combine the two technologies. The joint solution made possible by today’s agreement from Sundance and Celoxica uses C-based ESL tools. These enable system optimizations employing a comprehensive array of off-the-shelf modules and systems to address the critical issues of hardware/software co-design, DSP/FPGA integration, power utilization and cost reductions from design conception through to deployment.
"System designers commonly choose between DSP for signal processing systems and FPGAs to implement complex algorithms and signal processing systems," said Phil Bishop, president and CEO of Celoxica. "Combined they can offer a compelling solution for optimization of power, performance and flexibility. The key to unlocking this potential is providing design ease-of-use from both the DSP and FPGA perspectives."
"Many of our customers have already moved to model-based design and IP reuse to help streamline design and boost productivity," said Flemming Christensen, managing director of Sundance. "With more and more effort now being placed on value-added IP and customization inside a mixed DSP/FPGA system, the addition of C-based design that tackles complex algorithm development in hardware and software is inevitable."
The result of this partnership is the development of algorithm acceleration solutions for vertical applications. These include C-based IP modules, optimized FPGA hardware accelerators, and reference board prototypes built on Sundance boards programmed using Celoxica software tools. The companies will initially focus their efforts on software-defined radio (SDR) and complex image processing, and will begin rolling out solutions in Q4/05 at the Global Signal Processing Expo (GSPx) in Santa Clara.
"With this improved design flow for DSP plus FPGA based systems, customers can more easily integrate the performance of TI DSP with FPGA based co-processors," explained Ram Sathappan, SDR business development manager, Texas instruments. "C-based design and synthesis for hardware and software in DSP/ FPGA based COTS systems will address the needs of a wide range of designers."
"Xilinx and our Alliance Program members are seeing increasing market acceptance of our FPGAs for a broad range of DSP applications. We are gratified that Celoxica and Sundance have combined their expertise to make DSP development more accessible to design engineers to further accelerate this growth." said Robert Bielby, Xilinx senior director for vertical markets and partnerships.
About Sundance
Sundance designs, develops, manufactures and markets high performance signal processing and reconfigurable systems for original equipment manufacturers in the wireless and signal processing markets. Leveraging its multiprocessor expertise and experience, Sundance provides OEMs with modular DSP and FPGA-based systems as well as data acquisition, I/O, communication and interconnectivity products that are essential to multiprocessor systems where scalability and performance are vital. With over fifty different modules and carriers for PCI, cPCI VME and stand-alone platforms, Sundance is a solution provider to semiconductor, pharmaceutical and factory automation industries. The company was founded in 1989 by the current directors, is a member of the TI Third Party Network, Xilinx Xperts and MathWorks' Connection programs. For more information visit: www.sundance.com.
About Celoxica
An innovator in Electronic System Level (ESL) design, Celoxica is turning software into silicon by supplying the design tools, boards, IP and services that enable the next generation of advanced electronic product design. Celoxica technology raises design abstraction to the algorithm level, accelerating productivity and lowering risk and costs by generating semiconductor hardware directly from C-based software descriptions. Adding to a growing installed base, Celoxica provides the world's most widely used C-based behavioural design and synthesis solutions to companies developing semiconductor products in markets such as consumer electronics, defence and aerospace, automotive, industrial and security. For more information visit: www.celoxica.com.
|
Related News
- Silistix CHAINarchitect Bridges Gap Between Conventional and Leading-Edge Interconnect Methodologies
- Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments
- PGC Adopts S2C's FPGA-based ESL Tools to Streamline Front-End Design Service Flow
- ESL Design Targets Convergent DSP and FPGA
- Xilinx tool bridges gap between PLDs and DSPs
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |