Ziptronix Produces World's First Three-Dimensional System-on-Chip
MORRISVILLE, N.C.--Sept. 26, 2005--Turning industry vision to reality, Ziptronix, a leader in innovative semiconductor 3D technology, has built the world's first three-dimensional System-on-Chip (3D SoC) as a demonstration for a major networking technology customer for use in the development of wireless communication applications. Ziptronix' innovative 3D technology provides a viable, alternative to traditional System-on-Chip (SoC) and System-in-Package (SiP) technologies.
Ziptronix' new 3D SoC device, built using the company's proprietary ZiROC and ZiCON(R) technologies, combines memory, microprocessor and programmable logic die into a single, multi-level, silicon die measuring 280mm squared and the second level measuring just 0.03mm in height. This demonstration validates Ziptronix' core capabilities in dielectric covalent bonding and die thinning.
"The Ziptronix 3D SoC methodology helps customers with difficult size challenges," Phil Nyborg, President and CEO of Ziptronix, said. "Ziptronix has dedicated itself to bringing the most advanced System-on-Chip integration technologies to market - and our 3D SoC device testifies to our success. In terms of form factor and system value, Ziptronix offers a new paradigm in the way the industry can design and build baseline devices for many technology segments, such as communications, embedded systems and consumer electronics."
Ziptronix Technology
Ziptronix produced the world's first 3D SoC by applying its physical bonding and device interconnect technologies, which make vertical integration possible. The resulting 3D IC demonstrates that die-to-wafer bonding and die thinning yield working silicon. ZiROC bonding technology offers an adhesive-free methodology that forms covalent bonds directly between silicon oxide coated die using commonly available semiconductor manufacturing equipment and techniques. Using off-the-shelf components and employing die-scale integration, the time-to-market design cycle of 12-14 months for traditional SoC devices is reduced to six months.
"The validation of this Ziptronix second-generation device establishes credibility for 3D SoC - and opens the door to the next wave of system integration at the IC level," said Nyborg. "Ziptronix' three-dimensional integration technology can be used to realize devices with 2-billion plus transistors in the smallest possible footprint."
"This development demonstrates our expertise and focus in 3D IC technology and coincides with the initiation of our commercial rollout. Within our licensing business model, Ziptronix is engaging with a select group of initial partners adopting 3D IC design and manufacturing," said Nyborg.
About Ziptronix
Founded in October 2000, Ziptronix is a privately held company spun out from the Research Triangle Institute to commercialize ten years of research and development leading to the fabrication of three-dimensional integrated circuits. Its proven technology is being applied to development projects for major semiconductor manufacturers. Ziptronix has complete in-house fab capabilities for 3D technology development and 3D IC prototyping. Ziptronix corporate headquarters are in Morrisville, North Carolina. More information about Ziptronix is available through the World Wide Web at http://www.ziptronix.com.
|
Related News
- Atmel Produces Fourth-generation ARM-based System-on-Chip for M-Systems' Smart DiskOnKey Platform in Record Time
- SpringSoft's Siloti System Simplifies Visibility Automation and Debug Flow for System-on-Chip Verification
- Newport Media Unveils World's First 65nm System-on-Chip (SoC) for Japan/Brazilian ISDB-T Mobile TV
- TI Delivers Industry's First Sub-1 GHz RF System-on-Chip with Integrated USB Controller for Wireless Sensor Networks
- Newport Media Unveils World's First Mobile TV System-on-Chip (SoC) For ISDB-T Standard in Japan
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |