Renesas Technology Develops Capacitorless Twin-Transistor RAM, Enabling Faster, More Power-efficient Embedded Memory for SoC Devices

For 65nm and later-generation processes, the advanced memory has achieved fast operation (250MHz) and low active power (148mW) in a 2Mbit test chip

TOKYO, September 26, 2005 -- Renesas Technology Corp. today announced that it has developed a high-density capacitorless twin-transistor RAM (TTRAM) that achieves both high-speed operation and low power consumption. Researchers from Renesas unveiled details of the TTRAM in a paper presented the 2005 IEEE Custom Integrated Circuits Conference (CICC) in San Jose , California on September 20.
The memory design will allow fast, high-density storage to be embedded in power-efficient system-on-a-chip (SoC) devices built with 65nm (nanometer) generation and subsequent silicon-on-insulator (SOI) CMOS semiconductor processes. In a 2Mbit text chip fabricated with a 130nm SOI-CMOS process, the TTRAM has achieved 250MHz operation in continuous data output mode and 133MHz in random access operation, while dissipating an active power(1) of only 148mW, nearly 43 percent less than a conventional Renesas 130nm CMOS process embedded DRAM.

Test chip of Capacitorless Twin-Transistor RAM

While a DRAM cell requires a specially shaped capacitor, the TTRAM memory cell doesn't use a capacitor, so it is compatible with shrinks of process technology that make transistors smaller and faster. Thus, TTRAM has a clear technology roadmap for current and future manufacturing techniques. Also, on the 2Mbit test chip, the TTRAM cell size is 0.33ìm2, over 5 percent smaller than the 0.35ìm2 cell size of a 130nm CMOS process embedded DRAM test chip fabricated separately by Renesas.

Memory cell is a floating-body(2) type capacitorless design

In the new TTRAM memory cell, two transistors are serially connected on an SOI substrate. One is an access transistor, while the other is used as a storage transistor and fulfills the same function as the capacitor in a conventional DRAM cell. Data reads and writes are performed according to the conduction state of the access transistor and the floating-body potential state of the storage transistor. The fact that TTRAM memory cell operations don't require a step-up voltage or negative voltage, as DRAM cells do, makes the new cell design suitable for use with future finer processes and lower operating voltages.

With the Renesas TTRAM, a read signal from a memory cell appears as a difference in the transistor on-current. A current-mirror type sense amplifier detects this difference at high speed, using a reference memory cell that allows reliable identification of the 0 and 1 data levels. This reading method significantly decreases power consumption by eliminating the charging and discharging of bit lines, operations required for reading DRAM memory cells.

About Renesas Technology Corp.

Renesas Technology Corp. designs and manufactures highly integrated semiconductor system solutions for mobile, automotive and PC/AV markets. Established on April 1, 2003 as a joint venture between Hitachi, Ltd. (TSE:6501, NYSE:HIT) and Mitsubishi Electric Corporation (TSE:6503) and headquartered in Tokyo, Japan, Renesas Technology is one of the largest semiconductor companies in the world and the world's leading microcontroller supplier globally. Besides microcontrollers, Renesas Technology offers flash memories, system-in-package and system-on-chip devices, Smart Card ICs, mixed-signal products, SRAMs and more.
www.renesas.com