ASIC makers piece together their options

San Jose, Calif. — A decade ago, LSI Logic Corp. executives ushered reporters and analysts into a conference room to unveil the company's makeover and, by extension, a new way to tackle complex design. The scheme, called Coreware, sought to maintain the benefits of customized designs while adding standardized modules — cores — to ease the time-to-market and to lower costs. Invitees got Mr. Potato Head dolls that symbolized how different parts could be easily plugged into a base.

Today, Mr. Potato Head might just as well symbolize the ASIC industry itself. Under potentially lethal stress from spiraling investment demands, dwindling design-start numbers and escape-velocity growth in complexity, industry executives are plugging together pieces any way they can in an attempt to come up with something that looks like an attractive business model.

The desired result — a successful ASIC vendor at the 65-nanometer, 45-nm and later process nodes — is still a thing of unknown aspect. Some forms are gradually emerging from the experiments, but there are as yet no certainties.

The forces that threaten to crush the ASIC industry are well-documented. To begin with, there's the cost of process development. "We're talking $500 million to $1 billion to develop a new process today," estimated Tom Reeves, vice president at IBM Semiconductor Products and Solutions. Reeves is one executive who should know, having just spent that kind of money to develop 65 nm for IBM.

"That gets the process to the point where we can build things," Reeves said. "We still have maybe $100 million in front of us for developing IP [intellectual property] and design flows."

Moreover, those figures exclude the billion-dollar capital expenditures needed to build a production fab to exploit the process. "The economics of process development and capital investment require a very substantial mass," Reeves said.

Such pressures may force some companies to abandon fab strategies. That appears to have happened at LSI Logic, which announced last week that its 200-mm fab in Gresham, Ore., was for sale.

The decision was a long time coming. LSI was a pioneer of the fab-operating ASIC company. But as the Internet bubble burst in 2001 — even as a new, vastly expensive process node was approaching — it became clear that the Milpitas, Calif., company was not big enough to sustain its own manufacturing capability.

"You need $3 billion to $5 billion [in revenue] to support a fab, and they're sitting at $2 billion," said Dataquest vice president Bryan Lewis. "That's not going to cut it." Indeed, the writing may have been on the wall last year when LSI, for years among the top five in ASIC revenue, fell out of the top-10 vendors' list, according to Jordan Selburn of iSuppli Corp.

Nor is LSI Logic's situation unique. Agere Systems Inc. was in a similar box, said iSuppli analyst Len Jelinek, referring to Agere's decision to drop its manufacturing. "They have good expertise, but they had to stand back and ask themselves [the cost question]. The emerging trend is driven by the dollar."

Yet while the staggering costs would appear to push the industry toward accelerating disaggregation, ending with one big foundry that runs everyone's wafers with real economies of scale, complexity is pushing in just the opposite direction.

The interface between physical chip design and process engineering has disintegrated from a well-defined hand-off into a network of bidirectional feedback loops, according to industry experts. Physical designers must know intimate details of the process — often, information that foundries have been reluctant to disclose, even to their best customers. Conversely, process managers must know more and more about the design — its physical characteristics, its use of patterns and even its original intent.

Many have argued that this gives a natural advantage at advanced process nodes to integrated device manufacturers that own both the design team and the fab. "If you are designing a chip at 65 or 45 nm, you have to work with the guys who know the process," IBM's Reeves said.

This places great difficulties on companies that do disaggregate. "Frankly, I think at these geometries the fabless ASIC model will fail," Reeves said.

"It would be very tough to be a fabless ASIC company working in these advanced geometries today," said Chia Song Hwee, president and CEO of Singapore foundry Chartered Semiconductor Manufacturing. "You need that linking to the process."

Innovative models
But some companies have built successful businesses — albeit not huge ones — on the fabless ASIC model. And LSI Logic appears ready to try that approach.

One key part of the strategy is to avoid bleeding-edge processes and "science project" designs, both of which demand a level of intimacy between physical designers and fab engineers that may not be possible in the fabless model. LSI has always gone after leading-edge, high-margin design wins with a combination of excellent IP and hot processes. Whether it can sustain that sort of customer base with excellent IP and a more-conservative process strategy remains to be seen.

Fabless certainly isn't the only model being tried. Fujitsu Microelectronics is marching — alone — in exactly the opposite direction, unveiling last week a 65-nm process developed solely in-house.

Unlike LSI Logic, Fujitsu's IC group can depend on support from the giant parent corporation's server and mass-storage product divisions, which still see process-based differentiation in end systems as an important advantage. And the company is marshaling all its IP, software and application resources to create an offering that goes far beyond a pure-play foundry process.

"The days of a point semiconductor product are over," said Keith Horn, senior vice president of sales and marketing at Fujitsu Microelectronics America. "Today you have to provide much more of the total system, plus design support, IP and a road map to future process nodes."

In looking at the total package and developing a process by itself for its specific design needs, Fujitsu may have had a freedom that others lack. For example, the new 65-nm process is actually nearly a shrink of the company's 90-nm process. Except for limited use of a new low-k dielectric material, introduction of some strain engineering and the addition of a few pieces of equipment, the lines are the same, according to Fujio Nakanishi, general manager of the company's foundry/ASIC division.

By thinking of the 65-nm process as simply a part of a much wider system-engineering package, and by carefully supporting the needs of internal customers, Fujitsu may have been able to minimize both process development cost and initial capital expenditure. The process is running now on an existing 200-mm line, for instance. And Fujitsu may have minimized the complexity for design teams as well, by making few changes to the reportedly very easy-to-use 90-nm process.

We're all partners
Chartered Semiconductor touted a starkly different approach at its annual Technology Forum here last week. The company initially teamed with IBM on process development. The partnership grew to include Infineon Technologies, some work with Advanced Micro Devices and, recently, Samsung. The effort announced last week will offer GDSII-level compatibility among three 65-nm sources: Chartered, IBM and Samsung.

"We are at the point where a customer can work with our partners to produce a tapeout and then ask for bids from each of us on the wafers," said Chartered CEO Chia.

The aim of the giant collaboration is the same as what Fujitsu has accomplished on a smaller scale: a complete ecosystem of process, design interface, tool flows, software and application knowledge that can lead a customer directly from requirements to product. But in this case, different parts of that ecosystem will come from different companies, and manufacturing can take place at any of at least three fabs.

It is an audacious model — far beyond the sorts of process-development collaborations that have become common in advanced process engineering. "Each company [in the alliance] has its own 300-mm wafer fab," said iSuppli's Jelinek. This differs from the 90-nm Crolles, France, development effort by STMicroelectronics, Freescale and Philips, he continued, in that the Crolles partners are working only with Taiwan Semiconductor Manufacturing Co. "It's not seamless across multiple fabs," Jelinek said.

Whether such a broad alliance among companies that are to a certain extent direct competitors can succeed is an open question. Certainly in the case of IBM, Chartered and Samsung, there will be times of competitive bidding among the partners over a design that could have been done only with the close support of IBM's engineering teams. But Chia of Chartered believes the competition will not become predatory.

"Everyone is aware of the fact that we must have partnership to excel," he said. "And everyone is aware of the impact of their actions on the other partners."

Certainly, this grand alliance will not be the last new creature assembled at the hands of worried industry executives. Nor may it represent the final form for any of the partners today. But, just as certainly, it points in the direction a deeply stressed and yet essential industry is moving.

— Additional reporting by Patrick Mannion