NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Cadence Announces New Capabilities to Simplify and Accelerate PowerPC Design
SAN JOSE, Calif. , September 27, 2005 -- Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) today announced availability of a comprehensive set of services for SoC designers embedding PowerPC cores, including silicon validation of a new custom-synthesized design approach. The new approach results in up to a 30 percent increase in processor speed and a 40 percent reduction in chip area.
Developed in close collaboration with IBM, the custom-synthesized approach provides a new schedule-performance tradeoff point for performance-minded SoC designers embedding PowerPC cores. It advances PowerPC portability in markets such as consumer and networking, where processor speed and area results achievable with a full-synthesis approach may fall short, yet the performance of a full-custom approach is prohibited by time-to-market constraints.
"The Power architecture is critical to the computing and gaming markets and is rapidly expanding into broader applications, including emerging markets in SoC," said Tom Reeves, vice president of Semiconductor Products and Solutions at IBM. "We expect this new custom-synthesized approach from Cadence, coupled with their expertise in design services, to help drive increased market adoption of the Power Architecture."
Compared to a full-synthesis approach, the Cadence custom-synthesized approach achieves a 20 to 30 percent increase in processor speed while reducing chip area by 40 percent. Cadence Engineering Services achieves these results using Cadence's Virtuoso custom design platform to do full-custom design on the eight to 10 design blocks that most affect timing, power and area, such as the demanding CAMRAMs on the PowerPC 440 core. The remaining blocks are designed using Cadence's RTL Compiler synthesis, which has provided market-leading results for cycle time and chip real estate in PowerPC applications.
"SOC designers select the PowerPC as their processor core for its high performance, small core area and low power features. Now they can have it ported to their choice of fab with no sacrifice in these features," said Tim Henricks, vice president for Cadence Engineering Services. "Through collaboration with IBM, we have developed PowerPC porting capabilities superior to straight synthesis approaches that provide the performance these designers demand."
The custom-synthesized approach for PowerPC designers was validated in silicon by using a PowerPC 440 on the TSMC 130-LV manufacturing process.
Cadence is taking a comprehensive approach to meeting the needs of PowerPC designers. Because software development consumes the most schedule time in complex SoCs with powerful microprocessors, Cadence is offering co-verification services based on the Palladium#174; emulation platform. This helps reduce time to market and schedule risk at the system level by allowing design teams to develop software in parallel with the SoC design.
"L-3 has experienced successful results running the IBM PowerPC with Cadence's Palladium emulator," said Jim Grace, vice president of business development, L-3 Communications, Interstate Electronics Corporation. "We are looking forward to working with IBM and Cadence as they continue developing preferred solutions for the PowerPC."
Cadence is a founding member of Power.org, an open standards community that will help IC designers develop system-on-chips (SoCs) using the IBM PowerPC Architecture. Power.org is dedicated to promoting the IBM PowerPC Architecture as the preferred open-standard hardware-development platform for electronic systems for markets such as consumer electronics, networking, storage, military and automotive.
About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Cadence and Xilinx Simplify SoC Development With Enterprise Verification Capabilities for FPGA Targeted Design Platforms
- Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications
- Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- Cadence Acquires Invecas to Accelerate System Realization
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |