ESL providers get practical
EE Times: ESL providers get practical | |
Richard Goering (10/17/2005 10:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=172300907 | |
A quiet shift is emerging in electronic system-level design. Rather than look to upend existing methodologies, ESL providers are moving toward practical tools that solve real and immediate problems. Two or three years ago, the debate was over whether RTL designers would abandon VHDL and Verilog and move up to C-language design. Designers recoiled at the prospect. That debate has now largely gone away, although some large consumer design companies are starting to use C language synthesis. Today, SystemC is becoming widely adopted for transaction-level modeling. The purpose is to speed verification and architectural modeling, not to replace RTL design with something new. SystemC has thus come to address an immediate problem: RTL simulation is too slow. One practical ESL tool is Calypto Design Systems' SLEC. This sequential equivalency checker can verify that an RTL block is functionally equivalent to a higher-level block and that two sequentially different versions of an RTL block are equivalent. No need to change methodologies or languages, or even go above RTL. Other examples AccelChip's DSP Synthesis works from Matlab descriptions and recently added a capability that can automatically infer the macroarchitecture for mathematical functions for which it produces RTL code. No new language here; Matlab already has tens of thousands of users. If a designer can look at a tool and say, "Hey, I can understand that," it has a chance. There's little interest in labels like ESL, and less in changing methodologies-but lots of interest in anything that helps solve a problem. Richard Goering is Design Automation editor for EE Times. Send comments and questions to rgoering@cmp.com.
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