Altera's New Stratix II GX FPGAs With Embedded Transceivers Deliver Superior Signal Integrity

San Jose, Calif., October 24, 2005—Altera Corporation (NASDAQ:ALTR) today launched the Stratix® II GX family, its third generation of FPGAs with embedded serial transceivers. Designed to deliver superior signal integrity, Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers. Stratix II GX FPGAs combine the industry’s fastest and highest-density FPGA fabric with up to 20 low-power transceivers that operate between 622 Mbps to 6.375 Gbps to meet the requirements of high-speed designs of today and tomorrow.

Altera carefully selected the data range of the Stratix II GX transceivers based on customer requirements and future protocol roadmaps. The transceiver blocks provide complete support for a number of widely used protocols, including PCI Express, serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, SerialLite II, Serial RapidIO™, and Common Electrical Interface 6 Gbps Long Reach and Short Reach (CEI-6G-LR/SR), saving valuable logic resources and simplifying protocol support. Additionally, designers can complete their designs quickly and efficiently by utilizing Altera’s comprehensive system solutions that include intellectual property (IP), system models, reference designs, signal integrity tools, and supporting collateral.

Stratix II GX Features

Stratix II GX FPGA features help designers simplify the complex task of designing systems that use high-speed protocols. These features include:

• Multi-Gigabit Transceiver Blocks: Stratix II GX FPGAs provide up to 20 full-duplex channels operating between 622 Mbps and 6.375 Gbps natively and down to 270 Mbps using over-sampling techniques.

• Signal Integrity: Stratix II GX transceivers optimize the data eye opening using on-chip, dynamically programmable transmit pre-emphasis, receive equalization and output voltage control. In addition, through enhanced packaging and chip-design optimization techniques, standard I/Os are designed to provide best-in-class signal integrity.

• Low-Power Transceivers: Stratix II GX FPGA transceivers consume only 225 mW per channel at 6.375 Gbps, less than half that of the nearest competing FPGA solution.

• Flexible Transceiver PLL & Clocking Modes: Stratix II GX FPGAs arrange transceivers in a quad implementation. Each quad can be driven by two different clock sources each with access to a high-speed and a low-speed phase-locked loop (PLL). This combination of clocks and PLLs supports four different data rates and dramatically reduces power dissipation compared to the single PLL implementation found in competing devices.

• Up to 132,540 Equivalent Logic Elements (LEs) and up to 6.7 Mbits of Embedded Memory: The Stratix II GX devices’ high-density and embedded memory complement the bandwidth and performance of the device transceivers.

• Industry-Leading FPGA Architecture: Built on TSMC’s industry-leading, production-qualified, 90-nm process technology, the Stratix II GX family is based on the same FPGA fabric as the Stratix II FPGA family that offers unparalleled, and proven, density, performance, logic efficiency and design security.

“Customers are already leveraging the best-in-class signal integrity of the previous Stratix GX family and the performance and density advantages of the Stratix II family. In Stratix II GX FPGAs, we’ve extended the best features from these device families to meet the needs of the marketplace over the next several years,” said Danny Biran, vice president of product and corporate marketing at Altera. “System engineers using Stratix II GX FPGAs, along with the complete solutions that we’ve built around them, have a highly-efficient, low-risk development path for their high-speed designs.”

“Our goal is to deliver complete interconnect solutions that are robust and exceed demanding requirements for performance, reliability and value,” said Tom Pitten, vice president of engineering and marketing at Teradyne Connection Systems. “The work we have done with Altera in validating the entire interconnect continues to support this goal and provide system designers with solutions of exceptional signal integrity at leading-edge data rates.”

“Our collaboration with Altera in developing and correlating tools that enable modeling, design and manufacturing of robust serial interconnects has yielded excellent results,” said John D’Ambrosia, manager, semiconductor relations, Tyco Electronics. “Customers adhering to design methodology recommendations for Stratix II GX FPGAs and Tyco interconnect solutions can expect excellent signal integrity results.”

Availability & Pricing

Engineering samples of the first member of the Stratix II GX device family will be available in Q1 2006. Customers can start their Stratix II GX designs today using HSPICE models and Altera’s Quartus® II design software version 5.1. Volume prices start at $49 for the EP2SGX30CF780* device. For more information about Stratix II GX devices, visit www.altera.com/stratix2gx.

About Altera

Altera Corporation (NASDAQ:ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.

* 25K unit pricing in mid-2007

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