Motorola Ships World's First StarCore-Based DSP Product

AUSTIN, Texas, Oct. 11-- Motorola (NYSE: MOT) has announced that it is shipping samples of its MSC8101 digital signal processor (DSP) to early adopters. The innovative MSC8101, with network interface on chip, is the first DSP to use the SC140 core architecture developed by the StarCore alliance, a unique collaboration between Motorola and Lucent Technologies. Motorola is currently working closely with its strategic Alpha customers to expedite their time to market with products that incorporate the MSC8101.

The new MSC8101 DSP is well suited for all types of high-performance networking infrastructure DSP applications. Capable of operating at 1200 MMACS or 3000 RISC MIPS, the MSC8101 is the highest performance network-ready DSP on the market today. It offers low power dissipation in a small package, and is intended for applications requiring very high performance, large amounts of on-chip memory, and networking capabilities such as:

third-generation wireless infrastructure systems,

IP Telephony systems,

multi-channel modem banks, and

multi-channel xDSL.

MSC8101 early adopters -- leading communications companies around the world -- are working on system solutions for each of the target markets. From Asia, Japan, Europe, and the United States, this strategic group of customers is utilizing the unique performance and networking features of the MSC8101 to bring to market the next generation of infrastructure systems. These next generation systems are the vanguard in a revolutionary technological shift from circuit switched networks to packet switched networks.

DSPs are a key component of next generation systems with more channels and higher data rates, particularly with the move to third-generation (3G) systems. The required increase in DSP performance, for higher data rates and more channels per DSP, must be provided within the power per channel and cost per channel budgets of the overall solution.

The MSC8101 is the first product in the industry to offer a unique combination of DSP core, PowerPC[tm] interface, and Motorola's legacy Communications Processor Module (CPM) technologies all in a single integrated device. It is Motorola's unique position in the industry to offer such DigitalDNA[tm] capabilities for the communications and smart networking infrastructure markets.

With a 300MHz SC140 core, the MSC8101 offers four Arithmetic Logic Units (ALUs) providing 1200 MMACS (3000 RISC MIPS); a high-performance 150 MHz CPM programmable network protocol engine; 512KB (256K 16-bit words) of on-chip SRAM; a 100 MHz 64- or 32-bit PowerPC bus interface; and a programmable memory controller. On-chip peripherals such as a 300 MHz Enhanced Filter Coprocessor (EFCOP) and a powerful centralized DMA engine push performance even higher.

Delivering 4.2 million MAC operations per second (MMACs) per square millimeter of board space (or 10.4 RISC MIPS/mm2), the MSC8101 reaches new heights of performance density. The MSC8101 is the first StarCore-based DSP using 0.13 micron copper interconnect process technology developed in Motorola's DigitalDNA laboratories. It operates with a 1.5 V core power supply and an independent 3.3 V I/O power supply, dissipating a very low 500mW of power for the entire device. This combination of high performance and low power results in 0.16mW/MIPS power dissipation -- the lowest available on the market today for 1.5V core devices. It is designed to significantly reduce overall system power consumption and to allow use of a high-density 17mm x 17mm Flip-Chip Plastic Ball Grid Array (FC-PBGA) package.

One of the unique features of the MSC8101 is a programmable 32-bit RISC CPM. The CPM runs the networking protocol layers independent of the DSP core, enabling the MSC8101 to link directly to packetized backbones such as ATM and Fast Ethernet, as well as PCM highways such as E1/T1 and E3/T3. This may eliminate the need to have an additional network processor to perform this function. The powerful CPM engine is based on the same CPM technology from Motorola's popular PowerQUICC[tm] II (MPC8260) networking microcontrollers, used by today's top-ten networking companies.

To minimize time-to-market, the MSC8101 utilizes the SC140 core, the most compiler friendly DSP core in the industry, equipped with top-of-the-line software development tools. The baseline set of development tools includes the assembler, linker, C compiler, optimizer, simulator, debugger and other utilities all supplied by Metrowerks, a Motorola company, or Green Hills Software, Inc. The SC140 core was designed with C compilation in mind, so the compiler is engineered to provide unsurpassed efficiency in code optimization while maintaining optimum code density.

Motorola is also working with several other third-party companies to offer a wide choice of Integrated Development Environments (IDE) development tools, Real-Time Operating Systems (RTOS), optimized application software modules, and platform solutions. All of these are key factors in accelerating time to market designs based on the MSC8101. Examples of software modules include speech coders, echo cancellers, fax, and modem and will be available in both optimized C and assembly language for use in end-user applications.

To minimize system hardware interface development time, the MSC8101 has integrated a proven industry standard PowerPC (60x-compatible) bus. At 100 MHz bus operating speed and 64 or 32 bit width (programmable), the PowerPC bus enables the MSC8101 to easily hook to standard PowerPC bus devices, including PowerPC processors, peripherals, and shared memory subsystems. Additional system interface flexibility is provided through an enhanced 16-bit parallel Host Interface (HI16) which supports a variety of microcontroller, microprocessor, and DSP bus interfaces in conjunction with the PowerPC bus interface.

Infrastructure systems are driven by performance density. To minimize board space requirements, the MSC8101 integrates 512KB (4M bits) of on-chip zero-wait-state memory, which is designed to hold the program and data required in many of the target applications. This on-chip memory may eliminate or reduce accesses to off-chip memory, increasing system performance and lowering system power consumption, cost, and board space.

To maximize the number of channels each MSC8101 can process, the device integrates the EFCOP, already proven on Motorola's popular DSP56307 and DSP56311, to boost performance in filtering operations vital to such DSP tasks as echo cancellation. A sophisticated 16-channel DMA engine offloads the core from all data shuttling in the system.

Motorola is now working to introduce additional DSPs based on the SC140 core architecture, which will bring the level of performance to new heights.

Pricing and Availability

The expected sample date for general market availability is Q3 2001, with Motorola suggested resale pricing from sub $100.

Additional Information

Additional information on this announcement can be found at http://www.motorola-dsp.com.

About StarCore

Based in Atlanta, Georgia, the StarCore Joint Design Center is a cooperative research and development initiative between Lucent Technologies and Motorola created to define next-generation digital signal processor (DSP) core technologies. StarCore designs superior DSP architectures, cores, and development tools for the communications, consumer electronics and transportation industries. More information about StarCore is available at http://www.starcore-dsp.com.

About Motorola

As the world's #1 producer of embedded processors, Motorola's Semiconductor Products Sector offers multiple DigitalDNA[tm] technologies which enable its customers to create "smart" products and new business opportunities in the networking and computing, wireless communications, transportation, and imaging and entertainment markets. Motorola's worldwide semiconductor sales were $7.4 billion (USD) in 1999. http://www.motorola.com/semiconductors

Motorola, Inc. (NYSE: MOT) is a global leader in providing integrated communications solutions and embedded electronic solutions. Sales in 1999 were $33.1 billion. http://www.motorola.com

MOTOROLA, the Stylized M Logo and all other trademarks indicated as such herein are trademarks of Motorola, Inc. ®Reg. U.S. Pat. & Tm. Off." All other product or service names are the property of their respective owners.

SOURCE Motorola SPS

CONTACT: Readers, David Baczewski, 512-933-6911, david.baczewski@motorola.com, or Editorial, Mary Langen, 512-933-8758, r2aaap@email.sps.mot.com, both of Motorola; or Phyllis Grabot of MS&L Global Technology, 805-230-8205, pgrabot@msltech.com/