Silicon Laboratories Deploys CEVA-Teak DSP Core in Industry's Most Highly-Integrated Single-Chip Phone for GSM/GPRS Handsets
AeroFONE™ Single-Chip Phone utilizes superior power and performance advantages delivered by CEVA DSP core to perform integrated baseband processing
SAN JOSE, Calif. - November 1, 2005 - CEVA Inc., (NASDAQ: CEVA; LSE: CVA), the leading licensor of digital signal processors (DSP) cores, multimedia, GPS and storage platforms to the semiconductor industry announced today that Silicon Laboratories' has licensed and deployed the CEVA-Teak DSP core in the AeroFONE™ single-chip phone, the industry's most integrated, highest performance, easiest-to-use solution for GSM/GPRS handsets.
Existing cellphone IC solutions in the industry integrate some of the standard components that comprise the functionality of a handset, including digital baseband, RF transceiver, logic and analog functions. However, Silicon Laboratories' breakthrough innovations in chip design and integration has enabled them to take this process one step further, without compromising performance. By additionally integrating the analog baseband, power management unit (PMU), battery interface and charging circuitry into their single-chip phone, Silicon Laboratories has achieved a level of integration that no other solution in the market today can match.
Leveraging the superior processing performance and low-power requirements of CEVA-Teak to perform the baseband processing, AeroFONE offers a flexible and scalable platform for entry-level GSM/GPRS handsets without using expensive additional co-processors. The high performance of the AeroFONE single-chip phone also allows handset manufacturers to easily meet the stringent performance requirements of cellular network operators worldwide.
"The entry-level handset chip market is one of the most highly-competitive and high-volume markets in the industry," said Dan Rabinovitsj, vice president of Silicon Laboratories. "To achieve market penetration requires a solution which delivers exceptional performance with minimal power consumption and at a lowest possible total bill-of-materials. In the AeroFONE™ single-chip phone, the CEVA-Teak's low-power and high-performance baseband processing capabilities facilitated the successful inception of this product."
"The combination of CEVA's proven expertise in delivering high-performance, industry-leading DSP cores along with Silicon Laboratories' excellent track record in developing leading-edge handset technologies like AeroFONE, resulted in the creation of a truly unique offering for the handset market," said Gideon Wertheizer, CEO of CEVA. "This latest deployment of our CEVA-Teak DSP core further demonstrates the continued adoption of CEVA's technologies by leading semiconductor companies and underlines our position as the industry's leading licensor of DSP cores for wireless communications."
CEVA-Teak is a 16-bit fixed-point general-purpose DSP core. Its dual MAC architecture features high-performance, high flexibility and throughput for complex Digital Signal Processing implementations. The core is designed for low-power, speech and audio processing, multimedia and wireless communications (GSM, CDMA, EDGE, 3G, etc.), high-speed modems, advanced telecommunication systems, and various embedded control applications. CEVA-Teak is designed with consideration for low-power uses to achieve the best possible performance with the lowest possible power consumption. It makes the core suitable to a wide variety of battery-powered portable applications.
About AeroFONE™
The AeroFONE single-chip phone addresses the increasingly competitive handset market where board space is at a premium and total bill-of-materials (BOM) must enable a low cost handset without sacrificing performance.
- The AeroFONE single-chip phone supports the industry drive for high performance entry-level handsets.
- The AeroFONE single-chip phone does not compromise on RF performance and exhibits the same industry-leading sensitivity, blocking and transmit modulation spectrum characteristics of the Aero® II transceiver, all key requirements for entry-level handsets. Because newer deployments of network infrastructure in developing regions lack wide coverage, dropped calls are common if handsets do not have good sensitivity. Furthermore, high quality and reliability are important in emerging markets where new users will pay as much as one month's salary for a mobile phone. Return rates must be kept low in such markets as after-sales service is difficult and costly to implement for operators.
- Silicon Laboratories' approach to the single-chip phone offers a flexible and scalable platform for entry-level GSM/GPRS handsets without using expensive additional co-processors. Advanced multimedia capabilities can be supported with hardware co-processors allowing handset differentiation while saving costs.
- Silicon Laboratories' flexible software architecture uniquely enables handset developers to choose the software solution best for them.
- For more information visit www.silabs.com/AeroFONE
About CEVA, Inc.
For more information about CEVA, Inc, visit the about section of our website.
|
Ceva, Inc. Hot IP
Related News
- Atheros Communications Launches World's Most Integrated Single-Chip 802.11g Access Point Solution
- TTPCom and Silicon Laboratories partnership yields most integrated and proven GSM/GPRS solution
- Spreadtrum Launches World's First Chinese 3G Chipset Powered By CEVA-Teak DSP Core
- CSR launches the world's most highly integrated wireless single chip
- Japan Radio Co. Licenses CEVA-Teak DSP Core For Baseband Radio Communications
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |