CoWare SPW Advances Verification of 3G Wireless Modems; New HSDPA Models in 3GPP Library Reduce Design Risk for High-Speed Cellular Modems
"Designing an HSDPA system requires a myriad of system performance simulations," said Dr. Ahmad Vafaei, Senior Staff Engineer, InterDigital Communications Corporation. "We have been using CoWare's HSPDA Library as a reference tool for the 3GPP Release 5 standard. Having an executable reference for 50% of the modem functionality lets us focus on the differentiating components of our HSDPA algorithms."
"CoWare's wireless design solution goes beyond the proof of concept demonstrations other ESL solution providers are offering," said Johannes Stahl, Director Marketing, CoWare. "Our experienced team of wireless design experts continues to deliver detailed, high-quality libraries in lock step with the published standards. Whether you design a particular modem or you are working on software-defined radio, CoWare has the wireless models you need."
HSDPA - Complex, Adaptive Modulation and Coding, Hybrid ARQ
HSDPA delivers high data rates according to the transmission conditions by using adaptive modulation and coding (AMC) schemes. These cover a wide dynamic range in order to cope with the varying downlink radio and channel quality conditions at the handset. HSDPA adapts to these conditions by modifying the effective code rate, the modulation scheme, the number of codes used and power per code. The Hybrid ARQ (H-ARQ) mechanism is used in HSDPA to reduce the delay and increase the efficiency of the retransmitting data. Developing HSDPA receivers, which exhibit the desired performance using AMC and H-ARQ under varying channel conditions, is a design problem with an order of magnitude more scenarios to consider than the static modulation schemes used in previous 3GPP standards.
SPW Libraries Speed HSDPA Design
CoWare SPW is a complete platform for design and verification of DSP algorithms. Its up-to-date communications and multimedia source code libraries are transparently accessible, providing unmatched value for standards explanation and design. The 3GPP library is Release 5 compliant with the newly-added executable end-to-end system models of the HSDPA standard. Using the library, system engineers can rapidly create an accurate model of the system, incorporate their differentiating components, and then simulate the system under different scenarios to optimize the system performance. Leveraging SPW's high simulation speed, users can now explore many system options. And, with source code delivery and powerful PolyModel, designers can use the library as a starting point for detailed fixed-point design. Because the SPW HSDPA library was developed from active participation in the standardization process and with many years of experience developing 3G UMTS/WCDMA models, second-guessing of written standards proposals is eliminated.
Availability & Pricing
CoWare SPW with the 3GPP HSDPA Library and Communication Library is available today. For pricing and additional information on SPW and CoWare's other products, visit www.coware.com.
About CoWare
CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to "differentiate by design" through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge. CoWare's corporate investors include ARM Ltd. ((LSE:ARM); (Nasdaq:ARMHY)), Cadence Design Systems (NYSE:CDN), ST Microelectronics (NYSE:STM), and Sony Corporation (NYSE:SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services, visit www.coware.com.
|
Related News
- CoWare Advances Design of Ultra Wideband (UWB) Wireless Networking Products With Library Support Through Its Signal Processing Worksystem (SPW)
- Pro Design launches new CHIPit prototyping board for the verification of high-speed interfaces
- EVE's ZeBu Proven High-Speed Verification Solution for IBM PowerPC 405, 440 SoC Designs
- ProDesign Sets New Standards for High-Speed Verification with CHIPit Platinum V4
- MoSys and Open-Silicon Pound Tharas Systems Design Into Production; Tharas Systems Hammer(R) Verification Appliances Powered by Large Number of High-Speed 1T-SRAM Memory
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |