Ingot Announces New Memory Controller PHY IP

Santa Clara, Calif -- Nov 21, 2005 - Ingot Systems, the leading provider of Electronic Design Solutions, today announced the immediate availability of the IP4010, a new DDR/SDR SDRAM PHY solution. This new IP solution extend Ingot's offerings in the memory interface space and provides a proven building block for designers needing to create their own high-performance high-reliability memory interfaces. Designers looking for a complete solution can use the Ingot Systems IP4001 Intelligent Memory Manager instead of designing their own. Ingot’s PHY implementation is suited for a variety of applications and architectures. A detailed product brief is available on the Ingot Systems web site at www.ingotsys.com.

The IP4010 DDR/SDR SDRAM PHY is a flexible and advanced solution for ASIC and SoC designers who need to get the ultimate performance out of their memory interface using the least amount of silicon area. The IP4010 supports standard SDRAM, DDR SDRAM, or both. The PHY supports a wide variety of standards of each type, including single-data-rate JEDEC standard SDRAM and Mobile SDRAM, double-data-rate JEDEC standard DDR and DDR2 SDRAM, and Mobile DDR SDRAM.

IP4010 Feature Summary:

Complete SDR, DDR1, and DDR2 support
Fully digital design
400MHz clock speed (800 Mbps/pin data rate) in 90nm and 0.13um process.
Standard cell based DLL
Clean partitioning between scheduler and PHY allowing easy mix-and-match of controller and PHY from Ingot, customer, or third party
Support for every imaginable combination of data bus width, DRAM density, and 1 to 4 ranks
Low-power features such as powering down pads and disabling data capture on individual bytes with read data mask bits
Optional support for RDQS for deep rank configurations
DQS squelch that automatically matches pad and board trace latencies
“read data valid” indicator to core logic using programmable timing for minimum latency or calculated timing for maximum flexibility
PHY available as-is or customized to your requirement using Ingot’s design services

IP4010 Deliverables:

Either one of the following:

Hardened GDSII Macros, OR
Verilog netlist, PrimeTime timing scripts, and back-end support for layout
The PHY is typically delivered with data blocks separate from address/command to ease physical placement
Encrypted verilog simulation models
Full specification documentation
Complete testbench
Testplan and testbench documentation
DRAM protocol checkers
Support for spice simulation of I/O’s

Electronic Design Solutions

Traditional Design Service and IP companies take a ‘one-size fits all approach’ and typically offer a previously completed design (as an IP Core) as a solution to your design. It will require additional time and engineering effort to get it to ‘fit’ your requirements. Ingot has taken a more ‘custom tailored’ approach. We have used our extensive system design experience to create a unique infrastructure that allows us to tailor our target designs to your specific application. We call these design environments Electronic Design Solutions (EDS) Technology.

About Ingot Systems

Ingot Systems, Inc. is a premier Electronics Design Solutions company, headquartered in Santa Clara, California with global design centers located in India and the United States. Electronics Design Solutions Technology are an Ingot proprietary technology, which allows us to provide unprecedented levels of customizability, flexibility and quick time to market for our Design Services and IP Solutions.