IBM builds server line on Freeway MPU

IBM builds server line on Freeway MPU
By Margaret Quan, EE Times
October 8, 2000 (5:58 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001005S0034

NEW YORK — IBM Corp. this week formally launched a new mainframe-class 64-bit processor, dubbed the Freeway, and will reveal details of the device at next week's Microprocessor Forum in San Jose, Calif.

The Freeway processor forms the heart of the company's new highly redundant zSeries 900 e-servers, which one analyst described as "enormously scalable and enormously expensive."

With the Freeway and the zSeries 900 system design, IBM is attempting to recreate the speed, accuracy and redundancy of bipolar logic-based mainframes in a system form factor that's 1/20th the size.

To accomplish this goal, IBM used hardware microcode that deals with transient failures, plus a parallel and redundant architecture, high-density interconnect and sophisticated circuit-board technology.

"These are big systems, and they don't compare with what the other guys — HP, Sun, etc. — are doing in servers," said Martin Reynolds, director of tec hnology assessment at Dataquest Inc.

The foundation of the zSeries 900 e-servers — systems formerly branded as the S/390s — is a new generation of 64-bit microprocessors that features increased performance and bandwidth when compared with their 32-bit predecessors, the G5 and G6. IBM introduced those microprocessors in its S/390 models during the 1990s.

IBM has dedicated approximately 20 percent of the Freeway's functionality to issues of reliability, serviceability and availability. For example, the processor features duplicate instruction and execution units, parity in caches, and error correction in the L2 cache.

"Together, they provide the error detection and correction mainframes are known for," said Eric Schwarz, microprocessor logic design leader in IBM's server division in Poughkeepsie, N.Y.

The Freeway accommodates 24-, 32- and 64-bit addressing, which enables it to execute binary code created back in the 1960s.

The Freeway's design has been changed in several ways that improve its bandwidth and overall performance when compared with the earlier G5 and G6.

IBM engineers have split the cache into instruction and data caches to increase bandwidth as well as double the cache size, according to IBM's Schwarz.

IBM's engineers have also achieved a 3x to 4x performance improvement over the G6 with the addition of a data compression engine. At the same time they have quadrupled the size of the processor's branch target buffer so that it can fetch branch instructions faster. They have also increased the processor's decimal performance, a key enhancement for commercial applications that run Cobol.

The Freeway will initially operate at 770 MHz and will eventually run at a clock rate beyond 1 gigahertz. In March, IBM announced testing of the processor at 1 gigahertz, but faster versions of the chip will not be available until 2001.

The 47-million-transistor device will be manufactured in 0.18-micron process technology and will use IBM's seven-layer copper process on a 17.9 x 9.9-mm die.

While the Freeway's design is critical to the performance of the zSeries 900 server, its system architecture and packaging technology contribute equally to the high bandwidth and speed of the system.

Cramped module

The new server uses a large, 35-device multichip module (MCM) to improve multiprocessing capability. The MCM includes 20 Freeway processors and measures 5 x 5-inches. The MPUs are configured in a 16 plus four-way system, with 16 Freeway processors performing the application work, and four that can be used as I/O, coupling processors or spares. Running S/390 applications, the Freeway processors provide a total of 2,651 Mips, a 50 percent increase in performance over the earlier G6 processor in a 14-way S/390 configuration.

The multichip module's 15 other CMOS devices include eight L2 cache chips, two system controller chips, four memory I/O adapter chips and one clock chip. The MCM is mounted on a 101-layer, glass-ceramic backplane with six layers of t hin film. Within the MCM there are a total of 85,000 C4 device connections to the module leading to 4,226 I/O pins.

The MCM offers greater density, more wiring and more layers in the same 5 x 5-inch form factor used for the G6 module, and yields a 50 to 100 percent performance increase, said Herb Stoller, senior technical staff member at IBM Microelectronics Division in East Fishkill, N.Y.

To accommodate so many chips in a tight space, Stoller said the MCM required tighter ground rules than the G6 MCM, with more total nets and chips with tighter levels of interconnect. The result is an MCM with an I/O density that's 50 percent greater than the G6's .

The Freeway's design and the use of MCMs in the zSeries 900 allow several mainframes to be coupled together so that thirty-two 20-way processors can work together in a cluster of 640 processors.

A new 64-bit operating system, z/OS, takes advantage of the module's 64-bit real addressing capability and relieves memory constraints in applications. L ater versions of the z/OS will take advantage of its 64-bit virtual addressing capability. The zSeries 900 also supports Linux, which utilizes both 64-bit real and virtual addressing functions.

Prices for the zSeries 900 servers begin at $500 per Linux image, or $1.2 million for 2,500 instances of Linux.