Genesys Logic First to Market with PCI Express 4-lane 10Gbps PIPE PHY Chips
"The impact is profound." said Jerry Chen, Director of Marketing at Genesys Logic America. "For the first time the industry now has a 100% PCIe compliant 4-lane 10Gb/s PHY device. The GL9714 is an ideal solution for bandwidth-hungry FPGA applications, and designers no longer have compatibility issues."
GL9714 is supported by industry leaders worldwide. Zuken, a pioneer solutions company in Japan, successfully conducted the inter-operability tests between its advanced PCI Express x4 core logic and GL9714 earlier this year. The intended application was able to fully utilize GL9714's 10Gbps connection bandwidth to the host PC.
DDR PIPE design greatly enhances the usability of 4-lane PIPE PHY in FPGA designs. Running at 125MHz DDR for the 8-bit per lane interface, the design of GL9714 eases off the 250MHz high speed concern for most FPGA applications.
GL9714 is available immediately in LFBGA233 package format. Power consumption is in the 700mW range, with all 4 lanes running. For sales information, please contact sales@genesysamerica.com.
GL9714 and the formerly announced GL9711 1-lane version, fully comply with both the PCI Express™ Base Specification Revision 1.0a and the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel. Concatenation of GL9714 works well for 8/16/32 lanes configuration to meet the demand of various bandwidth requirements for networking, graphics, storage, and other high-speed applications.
|
Related News
- Genesys Logic First to Market with PCI Express PIPE PHY Chip
- OKI Electric Industry Selects Eureka Technology 4-Lane PCI Express IP Core
- Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP
- Altera and Genesys Logic Deliver PCI-SIG-Compliant x4 PCI Express Solution
- Programmable PCI Express Solution Announced by Lattice Semiconductor, Genesys Logic and Northwest Logic
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |