English
Genesys Logic First to Market with PCI Express 4-lane 10Gbps PIPE PHY Chips
San Jose, Calif -- November 30, 2005 -- Genesys Logic, Inc. (GLI) the high speed I/O communications specialist, today announced full production and availability of its PCI Express GigaCourier™ GL9714 integrated circuit (IC). The device provides PCB developers, for the first time, with an access speed of 10Gbps for various configurations of PIPE interfaces, including 250MHz/8-bit SDR and 125MHz/8-bit DDR PIPE.
"The impact is profound." said Jerry Chen, Director of Marketing at Genesys Logic America. "For the first time the industry now has a 100% PCIe compliant 4-lane 10Gb/s PHY device. The GL9714 is an ideal solution for bandwidth-hungry FPGA applications, and designers no longer have compatibility issues."
GL9714 is supported by industry leaders worldwide. Zuken, a pioneer solutions company in Japan, successfully conducted the inter-operability tests between its advanced PCI Express x4 core logic and GL9714 earlier this year. The intended application was able to fully utilize GL9714's 10Gbps connection bandwidth to the host PC.
DDR PIPE design greatly enhances the usability of 4-lane PIPE PHY in FPGA designs. Running at 125MHz DDR for the 8-bit per lane interface, the design of GL9714 eases off the 250MHz high speed concern for most FPGA applications.
GL9714 is available immediately in LFBGA233 package format. Power consumption is in the 700mW range, with all 4 lanes running. For sales information, please contact sales@genesysamerica.com.
GL9714 and the formerly announced GL9711 1-lane version, fully comply with both the PCI Express™ Base Specification Revision 1.0a and the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel. Concatenation of GL9714 works well for 8/16/32 lanes configuration to meet the demand of various bandwidth requirements for networking, graphics, storage, and other high-speed applications.
"The impact is profound." said Jerry Chen, Director of Marketing at Genesys Logic America. "For the first time the industry now has a 100% PCIe compliant 4-lane 10Gb/s PHY device. The GL9714 is an ideal solution for bandwidth-hungry FPGA applications, and designers no longer have compatibility issues."
GL9714 is supported by industry leaders worldwide. Zuken, a pioneer solutions company in Japan, successfully conducted the inter-operability tests between its advanced PCI Express x4 core logic and GL9714 earlier this year. The intended application was able to fully utilize GL9714's 10Gbps connection bandwidth to the host PC.
DDR PIPE design greatly enhances the usability of 4-lane PIPE PHY in FPGA designs. Running at 125MHz DDR for the 8-bit per lane interface, the design of GL9714 eases off the 250MHz high speed concern for most FPGA applications.
GL9714 is available immediately in LFBGA233 package format. Power consumption is in the 700mW range, with all 4 lanes running. For sales information, please contact sales@genesysamerica.com.
GL9714 and the formerly announced GL9711 1-lane version, fully comply with both the PCI Express™ Base Specification Revision 1.0a and the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel. Concatenation of GL9714 works well for 8/16/32 lanes configuration to meet the demand of various bandwidth requirements for networking, graphics, storage, and other high-speed applications.
|
||||||
Related News
- Genesys Logic First to Market with PCI Express PIPE PHY Chip
- OKI Electric Industry Selects Eureka Technology 4-Lane PCI Express IP Core
- Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP
- Altera and Genesys Logic Deliver PCI-SIG-Compliant x4 PCI Express Solution
- Programmable PCI Express Solution Announced by Lattice Semiconductor, Genesys Logic and Northwest Logic
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
|
E-mail This Article | 
|
|
Printer-Friendly Page |