English
Cambridge Consultants Unveils New 16-Bit XAP4 Processor Core
Low gate count, low power consumption and high code density for portable and cost sensitive applications
Cambridge UK and Boston MA, December 1, 2005 --- Cambridge Consultants has released a new 16-bit RISC microprocessor IP core, which it will feature at the Design & Reuse IP-SoC conference in Grenoble, France on December 7th and 8th 2005.
The all-new 16-bit XAP4 features a modern, high-performance RISC architecture with low gate count, low power consumption and high code density. It is optimized for use in cost and performance sensitive ASIC designs and is available for evaluation now. On a 0.18 micron CMOS fabrication process, XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over Cambridge Consultants' previous 16-bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.
The XAP4 has both 16-bit data and address buses and is capable of running programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12k gates for ASICs where die size and power consumption must be as small as possible. Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.
"This latest core fills a large gap in the market for ASIC processors," says Alistair Morfey, a technology director at Cambridge Consultants. "Many ASIC designs require good computing performance combined with low power and low cost. This is best met by a processor with high code density, which minimizes the cost and power of the program memory in ROM or Flash. Some 32-bit cores offer similar code density when run in their 16-bit mode, but designers are still paying for a 32-bit wide core and RAM inside their ASIC, which will cost twice as much in silicon as a 16-bit system. Every push and pop consumes extra power by doing 32-bit RAM accesses instead of 16-bit."
"In fact, there are probably hundreds of ASIC designs out there using more expensive 32-bit processor cores, when an advanced 16-bit core would do just as well," continues Morfey. "A 16-bit data bus offers adequate precision for most applications, and the XAP4 program size of 64 kbytes caters for a wide variety of real-world applications."
The 16-bit XAP4 is the latest addition to Cambridge Consultants' microprocessor core line-up. There is also the 32-bit XAP3 for more demanding applications, and in development is the XAP5 that also uses 16-bit data but extends the address bus to 24-bits, providing support for larger program sizes up to 16 Mbytes. All these processor cores include Cambridge Consultants' SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor's memory map for data acquisition while a system is running.
The architecture and design of the XAP3, XAP4 and XAP5 processors was conceived at Cambridge Consultants to fulfil the requirements of modern ASIC-based systems running code written by different programmers including real-time operating systems. All the processors include hardware support for privileged operating system modes where code running in user mode cannot corrupt supervisor or interrupt code. Code is position independent and there is also support for unaligned data access, making programs easy to port and quick to run. Most programs will be written in C and the processors feature direct support for many of the language constructs, which results in higher code density. There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.
All of Cambridge Consultants' XAP microprocessors are supported by its xIDE integrated software development and debug environment, which includes a programmer's editor, assembler, debug interface, instruction set simulator, project build manager and GCC compiler, which provides the path for programming in C++. xIDE is quick and easy to install and use on Windows PCs, with Linux/Unix and Mac OS versions also available. xIDE can be customized to add features specific to a licensee's ASIC or ASSP, and licensees can brand and deliver xIDE to their developers.
Other advanced technical features of the XAP3, XAP4 and XAP5 include: hardware support for operation as a slave processor when a master processor downloads a code image and bootstraps the XAP, support for multi-processor debug over SIF and architectures for combining XAP with Cambridge Consultants' APE signal processing engine, which offers a dynamic datapath routing capability.
Chris Turner, business development manager at Cambridge Consultants, said, "Licensees like the way XAP cores are delivered in Verilog RTL complete with software and debug tools. This user-friendly delivery format combined with our high level of customer support, including access to the XAP design team, means ASIC designers can apply XAP cores with confidence."
Turner also commented, "Cambridge Consultants' royalty-free business model also means that semiconductor companies adopting XAP processors can simplify their business and gain a significant increase in profitability over the production lifetimes of a range of products."
Details of the cores can be found at www.CambridgeConsultants.com/ASIC, including trial downloads of the xIDE software tools.
About Cambridge Consultants.
For over 40 years Cambridge Consultants has enabled its clients to turn business opportunities into commercial successes, whether launching first-to-market products, entering new markets or expanding existing markets through the introduction of new technologies. It develops breakthrough products, creates and licenses intellectual property, and provides business consultancy in technology critical issues for clients worldwide. With a team of over 200 engineers, scientists and consultants, in offices in Cambridge (UK) and Boston (USA), it is able to offer solutions across a diverse range of industries including healthcare, industrial and consumer products, automotive, transport, energy and wireless communications. www.CambridgeConsultants.com
Cambridge UK and Boston MA, December 1, 2005 --- Cambridge Consultants has released a new 16-bit RISC microprocessor IP core, which it will feature at the Design & Reuse IP-SoC conference in Grenoble, France on December 7th and 8th 2005.
The all-new 16-bit XAP4 features a modern, high-performance RISC architecture with low gate count, low power consumption and high code density. It is optimized for use in cost and performance sensitive ASIC designs and is available for evaluation now. On a 0.18 micron CMOS fabrication process, XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over Cambridge Consultants' previous 16-bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.
The XAP4 has both 16-bit data and address buses and is capable of running programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12k gates for ASICs where die size and power consumption must be as small as possible. Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.
"This latest core fills a large gap in the market for ASIC processors," says Alistair Morfey, a technology director at Cambridge Consultants. "Many ASIC designs require good computing performance combined with low power and low cost. This is best met by a processor with high code density, which minimizes the cost and power of the program memory in ROM or Flash. Some 32-bit cores offer similar code density when run in their 16-bit mode, but designers are still paying for a 32-bit wide core and RAM inside their ASIC, which will cost twice as much in silicon as a 16-bit system. Every push and pop consumes extra power by doing 32-bit RAM accesses instead of 16-bit."
"In fact, there are probably hundreds of ASIC designs out there using more expensive 32-bit processor cores, when an advanced 16-bit core would do just as well," continues Morfey. "A 16-bit data bus offers adequate precision for most applications, and the XAP4 program size of 64 kbytes caters for a wide variety of real-world applications."
The 16-bit XAP4 is the latest addition to Cambridge Consultants' microprocessor core line-up. There is also the 32-bit XAP3 for more demanding applications, and in development is the XAP5 that also uses 16-bit data but extends the address bus to 24-bits, providing support for larger program sizes up to 16 Mbytes. All these processor cores include Cambridge Consultants' SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor's memory map for data acquisition while a system is running.
The architecture and design of the XAP3, XAP4 and XAP5 processors was conceived at Cambridge Consultants to fulfil the requirements of modern ASIC-based systems running code written by different programmers including real-time operating systems. All the processors include hardware support for privileged operating system modes where code running in user mode cannot corrupt supervisor or interrupt code. Code is position independent and there is also support for unaligned data access, making programs easy to port and quick to run. Most programs will be written in C and the processors feature direct support for many of the language constructs, which results in higher code density. There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.
All of Cambridge Consultants' XAP microprocessors are supported by its xIDE integrated software development and debug environment, which includes a programmer's editor, assembler, debug interface, instruction set simulator, project build manager and GCC compiler, which provides the path for programming in C++. xIDE is quick and easy to install and use on Windows PCs, with Linux/Unix and Mac OS versions also available. xIDE can be customized to add features specific to a licensee's ASIC or ASSP, and licensees can brand and deliver xIDE to their developers.
Other advanced technical features of the XAP3, XAP4 and XAP5 include: hardware support for operation as a slave processor when a master processor downloads a code image and bootstraps the XAP, support for multi-processor debug over SIF and architectures for combining XAP with Cambridge Consultants' APE signal processing engine, which offers a dynamic datapath routing capability.
Chris Turner, business development manager at Cambridge Consultants, said, "Licensees like the way XAP cores are delivered in Verilog RTL complete with software and debug tools. This user-friendly delivery format combined with our high level of customer support, including access to the XAP design team, means ASIC designers can apply XAP cores with confidence."
Turner also commented, "Cambridge Consultants' royalty-free business model also means that semiconductor companies adopting XAP processors can simplify their business and gain a significant increase in profitability over the production lifetimes of a range of products."
Details of the cores can be found at www.CambridgeConsultants.com/ASIC, including trial downloads of the xIDE software tools.
About Cambridge Consultants.
For over 40 years Cambridge Consultants has enabled its clients to turn business opportunities into commercial successes, whether launching first-to-market products, entering new markets or expanding existing markets through the introduction of new technologies. It develops breakthrough products, creates and licenses intellectual property, and provides business consultancy in technology critical issues for clients worldwide. With a team of over 200 engineers, scientists and consultants, in offices in Cambridge (UK) and Boston (USA), it is able to offer solutions across a diverse range of industries including healthcare, industrial and consumer products, automotive, transport, energy and wireless communications. www.CambridgeConsultants.com
|
||||||
Related News
- Cambridge Consultants XAP5 core sets new standard for 16-bit processors
- Brite Launches High-Precision 16 bit SAR ADC
- Deal enables MOSIS to offer XAP 16-bit processors
- CMX Systems announces unique, embeddable SNMP functionality for CMX-MicroNet TCP/IP stack for 8-bit, 16-bit and DSP processors
- Embedded 16-bit MPU Market Headed for Downturn in 2005
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |