English
External IP: Who are decision makers?
Ron Wilson, EE Times
(12/12/2005 9:00 AM EST)
The first question to ask in examining how design teams select intellectual property is who does the selecting. And just asking respondents about themselves gave us our first big surprise in the study. We sent out invitations to a cross-section of design and verification engineers and their managers. Normally, when we are studying a question that is not of great concern to managers, those busy folks will mostly not respond. But this subject was different.
It was not different in overall statistics, however. In fact, design team size — a mean of roughly 13 — was about normal.
Further, as we expected, the average size of designs appears to be creeping up: Our study found an average of 5.3 million two-input NAND equivalent gates. But it would not be accurate to say that IP selection is solely the problem of large system-on-chip designs. Fully a fifth of respondents said their most recent design was in the under-100k-gate range.
Nor is IP selection an issue only in high-volume designs. More than half of the respondents said they expected to ship fewer than 10,000 units of their chip. Many of those low-volume designs are probably targeted to FPGAs rather than ASICs.
That said, our respondent demographics were a dramatic departure from the survey norm. Hardware engineers, their direct managers and project leaders made up about 70 percent of respondents. But system architects — those elusive figures behind the curtain who rarely respond to any survey — and corporate managers together made up a quarter of the respondents, an unprecedented number.
(12/12/2005 9:00 AM EST)
The first question to ask in examining how design teams select intellectual property is who does the selecting. And just asking respondents about themselves gave us our first big surprise in the study. We sent out invitations to a cross-section of design and verification engineers and their managers. Normally, when we are studying a question that is not of great concern to managers, those busy folks will mostly not respond. But this subject was different.
It was not different in overall statistics, however. In fact, design team size — a mean of roughly 13 — was about normal.
Further, as we expected, the average size of designs appears to be creeping up: Our study found an average of 5.3 million two-input NAND equivalent gates. But it would not be accurate to say that IP selection is solely the problem of large system-on-chip designs. Fully a fifth of respondents said their most recent design was in the under-100k-gate range.
Nor is IP selection an issue only in high-volume designs. More than half of the respondents said they expected to ship fewer than 10,000 units of their chip. Many of those low-volume designs are probably targeted to FPGAs rather than ASICs.
That said, our respondent demographics were a dramatic departure from the survey norm. Hardware engineers, their direct managers and project leaders made up about 70 percent of respondents. But system architects — those elusive figures behind the curtain who rarely respond to any survey — and corporate managers together made up a quarter of the respondents, an unprecedented number.
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