UMC Develops Ultimate Spacer Process to Enhance MOSFET Device Performance for 65nm and Beyond
HSINCHU, Taiwan, December 7, 2005 -- UMC (NYSE: UMC, TSE: 2303), a world leading semiconductor foundry, today announced that its Central Research and Development Division (CRD) has successfully developed an Ultimate Spacer Process (USP) technology that simultaneously enhances NMOS and PMOS device performance. Devices fabricated at UMC using USP exhibited drive current improvements of 15% for NMOS and 7% for PMOS, while maintaining overall process simplicity. This accomplishment is instrumental in achieving performance improvement during increasingly difficult CMOS scaling situations.
"Seeking ways to enhance electron and hole mobility is a major focus for device development at UMC," said Dr. Mike Ma, deputy division director of Exploratory Technology for the Central Research and Development division at UMC. "The USP technology enables UMC to provide an extra performance improvement option to complement our other mobility enhancement technologies. With only one additional process step inserted, USP also delivers a manufacturability advantage over other strained silicon technologies."
In addition, the performance advantage of USP can be leveraged with other mobility enhancement techniques; combining USP with substrate orientation engineering resulted in a 35% PMOS drive current enhancement. This USP technology has also been successfully deployed in a customer FPGA product, resulting in a 15% speed improvement without compromising yield and reliability performance. This confirms the readiness of applying USP technology for 65nm mass production and beyond.
UMC will present a detailed report of this technology at the "2005 IEEE International Electron Devices Meeting" in Washington, D.C. on December 7.
About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume production 90nm, industry-leading 65nm, and mixed signal/RFCMOS. UMC's 10 wafer manufacturing facilities include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 10,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.
|
Related News
- Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem
- M31 Technology Develops SRAM Compiler IP on TSMC's 28nm Embedded Flash Process Technology Providing High Performance and Low Power Solutions
- UMC to Develop 65nm BSI CMOS Image Sensor Process with STMicroelectronics
- SpringSoft, UMC Support Custom Chip Design with 65nm Process Design Kit
- Faraday Offers the First Memory Compiler in UMC 65nm LL Process
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |