English
Memories look to new materials set
David Lammers, EE Times
(12/19/2005 10:00 AM EST)
Austin, Texas — Over the last five years, changes to logic devices have grabbed much of the industry's attention, as copper, low-k dielectrics and strained silicon were introduced to keep scaling on track. Now, memories are set to undergo an equally dramatic series of materials and design changes, ranging from new dielectrics in DRAM and flash to SRAMs with eight transistors per cell, said participants at the recent International Electron Devices Meeting in Washington.
The chip industry overall achieved about 7 percent growth this year, largely due to strong sales of NAND flash memories. NAND cells are small and inexpensive to make, and companies making DRAMs can easily adapt their DRAM manufacturing processes to NAND. But as NAND cells become smaller, they tend to interfere with their neighboring cells. Also, reliability is a major challenge: The floating gate will soon have only about 1,000 electrons to store each bit, declining to only about 100 electrons at the 30-nanometer node. At IEDM, participants at an evening panel on nonvolatile memory scaling were in rough agreement that floating-gate flash will need to be overhauled at the 32-nm node, coming in at the end of this decade.
Albert Fazio, director of flash memory technology development at Intel Corp., said that flash must undergo "real structural change," probably at the 22-nm node. "Few people in the industry realize that compared with logic, flash uses an order-of-magnitude fewer electrons for data retention," he said.
"Adjacent-cell interference will require a high-k interpoly dielectric as we make the floating gate thinner," said Toshitake Yaegashi, a NAND engineering manager at Toshiba Corp. "At Toshiba, we believe the reliability issue is not as severe as the adjacent-cell coupling issue."
During the nonvolatile-memory sessions at IEDM, Kinam Kim, memory development manager at Samsung Electronics Co. Ltd., described a new dielectric and gate electrode structure, called Tanos, which Samsung has demonstrated in a 4-Gbit NAND cell. The dielectric combines silicon dioxide with nitrogen and aluminum oxide, and works with a gate electrode made of tantalum nitride.
(12/19/2005 10:00 AM EST)
Austin, Texas — Over the last five years, changes to logic devices have grabbed much of the industry's attention, as copper, low-k dielectrics and strained silicon were introduced to keep scaling on track. Now, memories are set to undergo an equally dramatic series of materials and design changes, ranging from new dielectrics in DRAM and flash to SRAMs with eight transistors per cell, said participants at the recent International Electron Devices Meeting in Washington.
The chip industry overall achieved about 7 percent growth this year, largely due to strong sales of NAND flash memories. NAND cells are small and inexpensive to make, and companies making DRAMs can easily adapt their DRAM manufacturing processes to NAND. But as NAND cells become smaller, they tend to interfere with their neighboring cells. Also, reliability is a major challenge: The floating gate will soon have only about 1,000 electrons to store each bit, declining to only about 100 electrons at the 30-nanometer node. At IEDM, participants at an evening panel on nonvolatile memory scaling were in rough agreement that floating-gate flash will need to be overhauled at the 32-nm node, coming in at the end of this decade.
Albert Fazio, director of flash memory technology development at Intel Corp., said that flash must undergo "real structural change," probably at the 22-nm node. "Few people in the industry realize that compared with logic, flash uses an order-of-magnitude fewer electrons for data retention," he said.
"Adjacent-cell interference will require a high-k interpoly dielectric as we make the floating gate thinner," said Toshitake Yaegashi, a NAND engineering manager at Toshiba Corp. "At Toshiba, we believe the reliability issue is not as severe as the adjacent-cell coupling issue."
During the nonvolatile-memory sessions at IEDM, Kinam Kim, memory development manager at Samsung Electronics Co. Ltd., described a new dielectric and gate electrode structure, called Tanos, which Samsung has demonstrated in a 4-Gbit NAND cell. The dielectric combines silicon dioxide with nitrogen and aluminum oxide, and works with a gate electrode made of tantalum nitride.
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