NEC Develops Multicore Processor Technology Enabling Automatic Parallelization of Application Programs
Tokyo, December 19, 2005 --- NEC Corporation today announced that it has succeeded in the development of multicore processor technology capable of performing automatic parallelization of application programs, without modifying them.
Key features of the multicore processor technology
(1) | An automatic parallelizing compiler, capable of effective extraction of parallelism from an application program utilizing its profile information (1*). |
(2) | An additional instruction-set, designed to minimize parallelization overheads. |
(3) | Processor architecture, which efficiently handles speculative execution (2*). |
(4) | Implementation realized by a simple extension to conventional processors. |
The distinctive feature of this new technology is the ability of the automatic parallelizing compiler that utilizes profile information to aggressively exploit parallelization patterns, which are effective for accelerating the speed of application programs. In addition, although the parallelization is speculative, the speculation is almost always completely accurate. The speculation hardware works as a safety net by handling any rare misses, guaranteeing the correctness of the execution. This ensures that the compiler is not conservative in decisions concerned with these cases, resulting in an increase in the amount of parallelism exploited. The parallelism exploitation is supported by the speculative execution hardware that realizes efficient handling of detection of incorrect execution orders caused by the parallel execution of the program parts, cancellation of the incorrectly executed part, and re-execution of it. Moreover, the parallelization process can be performed in a practical period of time.
In an increasingly networked society, the need for enhanced functionality and performance of terminals such as mobile phones and information appliances, while maintaining a low level of power consumption, is growing. Recently, many system-on-chips (SoCs) employing multicore and multiprocessor technology have been introduced practically to meet this expanding demand. This technology deploys multiple processor cores on a chip and effectively utilizes these multiple resources by parallelizing application programs. However, parallelization with conventional multiprocessor technology requires the manual modification of application source programs. Manual labor increases the development and verification cost for software development, which is in turn made more complex by the growing size and complexity of the software itself. Therefore, multiprocessor technology, which can automatically parallelize application programs without manual modification, has been long sought after in this field. However, nobody has succeeded in bringing automatic parallelization technology to a practical stage to date.
NEC believes that its automatic parallelization technology is the first to be brought to a stage of practical use. This is supported by the fact that NEC has succeeded in operating this technology on a field-programmable gate array (FPGA). Moreover, its implementation has confirmed that only a marginal hardware extension is required and that application program speed is actually accelerated.
The newly developed technology realizes automatic parallelization of application programs and a dramatic reduction in time and cost of parallelization. In addition, we have observed cases where automatic parallelization accelerates the speed of programs at a greater rate than that of manual parallelization. For example, one test showed that manual parallelization of an application program took four months of time with one person carrying out the task, however, automatic parallelization cut this time to just three minutes with no manual labor involved at all. In addition, the application program that has been parallelized manually runs 1.95 times faster with four processors than the original application program running with one processor. However, the application program that has been parallelized automatically runs 2.83 times faster with four processors, which indicates that automatic parallelization achieves greater acceleration than manual parallelization. This shows that automatic parallelization facilitates development of software with high functionality and performance through multicore and multiprocessor technology, at lower cost over a shorter time frame. This will lead to the provision of terminals such as cellular phones and information appliances with enhanced functionality and performance.
NEC will continue to advance the research and development of its multicore processor technology toward early release of products incorporating it.
- About NEC Corporation
Notes
- (*1)
- Profile information: execution history of an application program.
- (*2)
- Speculative execution: executing a part of a program in a manner where its execution results can be canceled and it can be re-executed.
|
Related News
- Codasip announces three new RISC-V Application Processor Cores providing Multi-core and SIMD capability
- GreenWaves Technologies Unveils GAP8, the Industry's Lowest Power IoT Application Processor, Enabling Groundbreaking Embedded Artificial Intelligence at the Very Edge
- Socionext Develops New Large Scale, High Efficiency Distributed Processing Server, Fully Utilizing Multi-Core Processors
- Cavium Networks Announces Breakthrough Next Generation OCTEON II Multi-Core MIPS64 Internet Application Processor Family With 1 to 32 Cores
- NEC Develops Multicore-Based System LSI Platform for Reliable and High-Performance Ubiquitous Terminals
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |