Arithmatica Expands CellMath Tools Line with CellMath Optimizer for Silicon-Efficient Delivery of Datapath-Oriented Silicon IP
MENLO PARK, Calif.--Jan. 10, 2006--Arithmatica, Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, today expanded its CellMath tools line with CellMath Optimizer, providing silicon-efficient datapath re-use. Companies that rely on re-targeting IP that contains complex, high-performance datapaths can now do so with improved silicon results. CellMath Optimizer performance-tunes datapath-intensive IP for either new timing requirements in the original target process or when re-targeting for a new process and/or performance point. This re-captures the typical 10-20 percent performance loss when relying on RTL and traditional synthesis and avoids use of power-hungry gate sizing to close timing. CellMath Optimizer includes the following features:
- Automated architecture selection: the datapath architecture is optimized based on the user SDC-compatible timing constraints and target process defined by the user .lib file;
- Area and power optimizations: particularities of library are reflected in cell choice during re-mapping. Especially important for the power consumption profile of libraries which tend to differ significantly;
- Ease of use: embedded by using scripts within the IP vendors' standard IP offering so that users can maintain their existing flows and testbenches;
- Formal verification support: intermediate behavioral and gate-level models to ease formal verification.
Most IP is delivered or re-used as RTL, providing the SOC designer maximum flexibility in terms of process technology selection. However, this flexibility comes at significant cost for IP that contains complex, high-performance datapaths since the range of arithmetic architectures are limited to those supported within traditional RTL synthesis tools. Optimization, therefore, is limited during re-targeting to primarily logic optimization and gate sizing to achieve specific power, area and timing goals -- leading to performance and power results that fall short. Multiple customers have found that CellMath Optimizer closes this performance gap without upsizing gates which can lead to costly increases in power consumption. Imagination Technologies, a leader in embedded graphics processing, has successfully optimized their IP product delivery using CellMath Optimizer. Martin Ashton, Imagination's General Manager of PowerVR, stated: "Imagination Technologies provides advanced mobile graphics processor IP. We gained double benefit from Arithmatica's datapath design tools, using CellMath Designer in the design phase of our PowerVR SGX shader architecture to lower area and power and then using CellMath Optimizer to deliver our IP so that our licensees can optimize silicon-efficiency and performance in their target process technology. Overall we reduced die area significantly as well as ensured aggressive performance targets were met."
Tony Curzon Price, Arithmatica's CEO, said: "Datapath designs gain from architecture trades, but those trades cannot be made until the end application needs and process technology are known. Our CellMath datapath tools have given us some insight into these performance challenges when designing datapath circuits with re-use in mind. CellMath Optimizer addresses this performance gap by enhancing IP core delivery with self-synthesizing capabilities that re-capture the silicon-efficiency compromised in typical synthesis flows. With the strong demand for IP re-use within the consumer electronics market, we see CellMath Optimizer addressing 3D graphics, imaging, multimedia, embedded processing, and communications IP re-use and delivery. We are pleased that innovative technology companies like Imagination Technologies have improved their competitiveness by successfully deploying our newest CellMath tool."
Pricing and Availability
Arithmatica actively markets and supports its products in North America, Europe, Japan, Korea and Taiwan. CellMath Optimizer is production-released and term licensed for developers with volume redistribution terms for commercial IP companies and volume corporate users. U.S. single copy annual license fee is $19,000.
About Arithmatica
Arithmatica is the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, such as those used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing. Its unique technology, available through its tools products and design services, provides differentiated improvement to licensees' ICs. The company received its first venture funding in 2001 and is headquartered in Warwick, U.K., with sales and support operations in Menlo Park, Calif. For further information about how its silicon math solutions increase silicon-efficiency and boost productivity, please visit: www.arithmatica.com.
|
Related News
- Arithmatica Expands Global Sales Network to Europe to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs
- Arithmatica Expands Global Coverage to Meet Demand for Efficient Silicon Math in Consumer Electronics ICs
- Arithmatica Enters EDA Market with Proven Tools that Boost Silicon Efficiency by up to 40 Percent for Datapath-Intensive Applications
- MIPS Technologies, Inc. announces new MIPS-3D technology to provide silicon-efficient 3D graphics acceleration <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
- Silicon Image Expands MHL Product Line with Four New Products
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |