English
Leakage takes priority at 65 nm
Richard Goering, EE Times
(01/16/2006 10:00 AM EST)
As the first reports on 65-nanometer design come in from the field, the good news is that there don't appear to be any problems at 65 nm that weren't there are 90. The bad news is that some of the problems that plagued 90 nm get much worse at the new node.
Designers who have completed 65-nm projects generally identify leakage current as the biggest problem, and they're turning to a variety of strategies to manage power, including multiple voltage thresholds and voltage "islands."
"Clearly the threshold leakage and gate leakage are getting significantly worse. New design techniques have to be adopted," said Dermot Barry, general manager for the system IC business unit at design services firm Silicon & Software Systems (S3).
Design-for-manufacturability (DFM) also becomes a bigger issue at 65 nm because process variations worsen, sources said. And signal integrity problems grow as wiring gets denser.
On the manufacturing side, resolution enhancement technology (RET) becomes more complex at 65 nm, said Peter Rickert, technology development manager at Texas Instruments Inc. And process variations have much more impact. "A plus/minus 1-nm variation is a much higher percentage at 65 nm, where we might be talking about a 40-nm gate length, vs. 50 or 60 at 90 nm," Rickert noted.
(01/16/2006 10:00 AM EST)
As the first reports on 65-nanometer design come in from the field, the good news is that there don't appear to be any problems at 65 nm that weren't there are 90. The bad news is that some of the problems that plagued 90 nm get much worse at the new node.
Designers who have completed 65-nm projects generally identify leakage current as the biggest problem, and they're turning to a variety of strategies to manage power, including multiple voltage thresholds and voltage "islands."
"Clearly the threshold leakage and gate leakage are getting significantly worse. New design techniques have to be adopted," said Dermot Barry, general manager for the system IC business unit at design services firm Silicon & Software Systems (S3).
Design-for-manufacturability (DFM) also becomes a bigger issue at 65 nm because process variations worsen, sources said. And signal integrity problems grow as wiring gets denser.
On the manufacturing side, resolution enhancement technology (RET) becomes more complex at 65 nm, said Peter Rickert, technology development manager at Texas Instruments Inc. And process variations have much more impact. "A plus/minus 1-nm variation is a much higher percentage at 65 nm, where we might be talking about a 40-nm gate length, vs. 50 or 60 at 90 nm," Rickert noted.
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